powerpc/perf: POWER9 PMU stops after idle workaround

[sfrench/cifs-2.6.git] / arch / powerpc / kernel / idle_book3s.S

diff --git a/arch/powerpc/kernel/idle_book3s.S b/arch/powerpc/kernel/idle_book3s.S
index 5adb390e773bdd441ed0456eaed2511c094264a7..e6252c5a57a4a06f10bd13710ceecdcf72c3d26e 100644 (file)
--- a/arch/powerpc/kernel/idle_book3s.S
+++ b/arch/powerpc/kernel/idle_book3s.S
@@ -30,6 +30,7 @@
  * Use unused space in the interrupt stack to save and restore
  * registers for winkle support.
  */
+#define _MMCR0 GPR0
 #define _SDR1  GPR3
 #define _PTCR  GPR3
 #define _RPR   GPR4
@@ -272,6 +273,14 @@ power_enter_stop:
        b       pnv_wakeup_noloss
 
 .Lhandle_esl_ec_set:
+       /*
+        * POWER9 DD2 can incorrectly set PMAO when waking up after a
+        * state-loss idle. Saving and restoring MMCR0 over idle is a
+        * workaround.
+        */
+       mfspr   r4,SPRN_MMCR0
+       std     r4,_MMCR0(r1)
+
 /*
  * Check if the requested state is a deep idle state.
  */
@@ -450,10 +459,20 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
 pnv_restore_hyp_resource_arch300:
        /*
         * Workaround for POWER9, if we lost resources, the ERAT
-        * might have been mixed up and needs flushing.
+        * might have been mixed up and needs flushing. We also need
+        * to reload MMCR0 (see comment above). We also need to set
+        * then clear bit 60 in MMCRA to ensure the PMU starts running.
         */
        blt     cr3,1f
        PPC_INVALIDATE_ERAT
+       ld      r1,PACAR1(r13)
+       mfspr   r4,SPRN_MMCRA
+       ori     r4,r4,(1 << (63-60))
+       mtspr   SPRN_MMCRA,r4
+       xori    r4,r4,(1 << (63-60))
+       mtspr   SPRN_MMCRA,r4
+       ld      r4,_MMCR0(r1)
+       mtspr   SPRN_MMCR0,r4
 1:
        /*
         * POWER ISA 3. Use PSSCR to determine if we