Merge tag 'fscache-fixes-20141013' of git://git.kernel.org/pub/scm/linux/kernel/git...

[sfrench/cifs-2.6.git] / arch / powerpc / include / asm / opal.h

diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 86055e598269ebc9c4ba2c52ea3b6f59a27599e2..9124b0ede1fc7f531a97d369169706024741ce17 100644 (file)
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -135,6 +135,7 @@ struct opal_sg_list {
 #define OPAL_FLASH_MANAGE                      77
 #define OPAL_FLASH_UPDATE                      78
 #define OPAL_RESYNC_TIMEBASE                   79
+#define OPAL_CHECK_TOKEN                       80
 #define OPAL_DUMP_INIT                         81
 #define OPAL_DUMP_INFO                         82
 #define OPAL_DUMP_READ                         83
@@ -146,7 +147,9 @@ struct opal_sg_list {
 #define OPAL_GET_PARAM                         89
 #define OPAL_SET_PARAM                         90
 #define OPAL_DUMP_RESEND                       91
+#define OPAL_PCI_SET_PHB_CXL_MODE              93
 #define OPAL_DUMP_INFO2                                94
+#define OPAL_PCI_ERR_INJECT                    96
 #define OPAL_PCI_EEH_FREEZE_SET                        97
 #define OPAL_HANDLE_HMI                                98
 #define OPAL_REGISTER_DUMP_REGION              101
@@ -199,6 +202,35 @@ enum OpalPciErrorSeverity {
        OPAL_EEH_SEV_INF        = 5
 };
 
+enum OpalErrinjectType {
+       OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR        = 0,
+       OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64      = 1,
+};
+
+enum OpalErrinjectFunc {
+       /* IOA bus specific errors */
+       OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR    = 0,
+       OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA    = 1,
+       OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR     = 2,
+       OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA     = 3,
+       OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR    = 4,
+       OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA    = 5,
+       OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR    = 6,
+       OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA    = 7,
+       OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR     = 8,
+       OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA     = 9,
+       OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR    = 10,
+       OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA    = 11,
+       OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR    = 12,
+       OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA    = 13,
+       OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER  = 14,
+       OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET  = 15,
+       OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR    = 16,
+       OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA    = 17,
+       OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER  = 18,
+       OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET  = 19,
+};
+
 enum OpalShpcAction {
        OPAL_SHPC_GET_LINK_STATE = 0,
        OPAL_SHPC_GET_SLOT_STATE = 1
@@ -356,9 +388,12 @@ enum OpalM64EnableAction {
 };
 
 enum OpalPciResetScope {
-       OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
-       OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
-       OPAL_PCI_IODA_TABLE_RESET = 6,
+       OPAL_RESET_PHB_COMPLETE         = 1,
+       OPAL_RESET_PCI_LINK             = 2,
+       OPAL_RESET_PHB_ERROR            = 3,
+       OPAL_RESET_PCI_HOT              = 4,
+       OPAL_RESET_PCI_FUNDAMENTAL      = 5,
+       OPAL_RESET_PCI_IODA_TABLE       = 6
 };
 
 enum OpalPciReinitScope {
@@ -819,6 +854,8 @@ int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
                                  uint64_t eeh_action_token);
 int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
                                uint64_t eeh_action_token);
+int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
+                           uint32_t func, uint64_t addr, uint64_t mask);
 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
 
 
@@ -887,6 +924,7 @@ int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
                            __be16 *pci_error_type, __be16 *severity);
 int64_t opal_pci_poll(uint64_t phb_id);
 int64_t opal_return_cpu(void);
+int64_t opal_check_token(uint64_t token);
 int64_t opal_reinit_cpus(uint64_t flags);
 
 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
@@ -924,6 +962,7 @@ int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
 int64_t opal_handle_hmi(void);
 int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
 int64_t opal_unregister_dump_region(uint32_t id);
+int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
 
 /* Internal functions */
 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,