Merge branch 'next-tpm' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...

[sfrench/cifs-2.6.git] / arch / parisc / kernel / entry.S

diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
index 0d662f0e7b70bd8e3684892d208096a8fa5492e8..1c60408a64ad3b46b3fd1fed63e96329f3221c8f 100644 (file)
--- a/arch/parisc/kernel/entry.S
+++ b/arch/parisc/kernel/entry.S
@@ -38,6 +38,7 @@
 #include <asm/ldcw.h>
 #include <asm/traps.h>
 #include <asm/thread_info.h>
+#include <asm/alternative.h>
 
 #include <linux/linkage.h>
 
@@ -186,7 +187,7 @@
        bv,n    0(%r3)
        nop
        .word   0               /* checksum (will be patched) */
-       .word   PA(os_hpmc)     /* address of handler */
+       .word   0               /* address of handler */
        .word   0               /* length of handler */
        .endm
 
@@ -426,8 +427,7 @@
        ldw,s           \index(\pmd),\pmd
        bb,>=,n         \pmd,_PxD_PRESENT_BIT,\fault
        dep             %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
-       copy            \pmd,%r9
-       SHLREG          %r9,PxD_VALUE_SHIFT,\pmd
+       SHLREG          \pmd,PxD_VALUE_SHIFT,\pmd
        extru           \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
        dep             %r0,31,PAGE_SHIFT,\pmd  /* clear offset */
        shladd          \index,BITS_PER_PTE_ENTRY,\pmd,\pmd /* pmd is now pte */
@@ -446,7 +446,6 @@
        .macro          L3_ptep pgd,pte,index,va,fault
 #if CONFIG_PGTABLE_LEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */
        extrd,u         \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
-       copy            %r0,\pte
        extrd,u,*=      \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
        ldw,s           \index(\pgd),\pgd
        extrd,u,*=      \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
@@ -464,7 +463,7 @@
        /* Acquire pa_tlb_lock lock and check page is present. */
        .macro          tlb_lock        spc,ptp,pte,tmp,tmp1,fault
 #ifdef CONFIG_SMP
-       cmpib,COND(=),n 0,\spc,2f
+98:    cmpib,COND(=),n 0,\spc,2f
        load_pa_tlb_lock \tmp
 1:     LDCW            0(\tmp),\tmp1
        cmpib,COND(=)   0,\tmp1,1b
@@ -473,6 +472,7 @@
        bb,<,n          \pte,_PAGE_PRESENT_BIT,3f
        b               \fault
        stw,ma          \spc,0(\tmp)
+99:    ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
 #endif
 2:     LDREG           0(\ptp),\pte
        bb,>=,n         \pte,_PAGE_PRESENT_BIT,\fault
@@ -482,15 +482,17 @@
        /* Release pa_tlb_lock lock without reloading lock address. */
        .macro          tlb_unlock0     spc,tmp
 #ifdef CONFIG_SMP
-       or,COND(=)      %r0,\spc,%r0
+98:    or,COND(=)      %r0,\spc,%r0
        stw,ma          \spc,0(\tmp)
+99:    ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
 #endif
        .endm
 
        /* Release pa_tlb_lock lock. */
        .macro          tlb_unlock1     spc,tmp
 #ifdef CONFIG_SMP
-       load_pa_tlb_lock \tmp
+98:    load_pa_tlb_lock \tmp
+99:    ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
        tlb_unlock0     \spc,\tmp
 #endif
        .endm