dvpe();
dmt();
- mips_mt_set_cpuoptions();
-
/* Put MVPE's into 'configuration state' */
set_c0_mvpcontrol(MVPCONTROL_VPC);
void __init plat_prepare_cpus(unsigned int max_cpus)
{
+ mips_mt_set_cpuoptions();
+
/* set up ipi interrupts */
if (cpu_has_vint) {
set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
* (unsigned long)idle->thread_info the gp
* assumes a 1:1 mapping of TC => VPE
*/
-void prom_boot_secondary(int cpu, struct task_struct *idle)
+void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
{
struct thread_info *gp = task_thread_info(idle);
dvpe();
evpe(EVPE_ENABLE);
}
-void prom_init_secondary(void)
+void __cpuinit prom_init_secondary(void)
{
/* Enable per-cpu interrupts */
(STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7));
}
-void prom_smp_finish(void)
+void __cpuinit prom_smp_finish(void)
{
write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
unsigned long flags;
int vpflags;
- local_irq_save (flags);
+ local_irq_save(flags);
vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */