Merge tag 'libnvdimm-for-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdim...

[sfrench/cifs-2.6.git] / arch / mips / kernel / r4k_fpu.S

diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 8e3a6020c613453fda948a33f4aa6435b9f79ad9..59be5c812aa28a321ee42cce82da569b7d27aa92 100644 (file)
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -86,150 +86,6 @@ LEAF(_init_msa_upper)
 
 #endif
 
-/*
- * Load the FPU with signalling NANS.  This bit pattern we're using has
- * the property that no matter whether considered as single or as double
- * precision represents signaling NANS.
- *
- * The value to initialize fcr31 to comes in $a0.
- */
-
-       .set push
-       SET_HARDFLOAT
-
-LEAF(_init_fpu)
-       mfc0    t0, CP0_STATUS
-       li      t1, ST0_CU1
-       or      t0, t1
-       mtc0    t0, CP0_STATUS
-       enable_fpu_hazard
-
-       ctc1    a0, fcr31
-
-       li      t1, -1                          # SNaN
-
-#ifdef CONFIG_64BIT
-       sll     t0, t0, 5
-       bgez    t0, 1f                          # 16 / 32 register mode?
-
-       dmtc1   t1, $f1
-       dmtc1   t1, $f3
-       dmtc1   t1, $f5
-       dmtc1   t1, $f7
-       dmtc1   t1, $f9
-       dmtc1   t1, $f11
-       dmtc1   t1, $f13
-       dmtc1   t1, $f15
-       dmtc1   t1, $f17
-       dmtc1   t1, $f19
-       dmtc1   t1, $f21
-       dmtc1   t1, $f23
-       dmtc1   t1, $f25
-       dmtc1   t1, $f27
-       dmtc1   t1, $f29
-       dmtc1   t1, $f31
-1:
-#endif
-
-#ifdef CONFIG_CPU_MIPS32
-       mtc1    t1, $f0
-       mtc1    t1, $f1
-       mtc1    t1, $f2
-       mtc1    t1, $f3
-       mtc1    t1, $f4
-       mtc1    t1, $f5
-       mtc1    t1, $f6
-       mtc1    t1, $f7
-       mtc1    t1, $f8
-       mtc1    t1, $f9
-       mtc1    t1, $f10
-       mtc1    t1, $f11
-       mtc1    t1, $f12
-       mtc1    t1, $f13
-       mtc1    t1, $f14
-       mtc1    t1, $f15
-       mtc1    t1, $f16
-       mtc1    t1, $f17
-       mtc1    t1, $f18
-       mtc1    t1, $f19
-       mtc1    t1, $f20
-       mtc1    t1, $f21
-       mtc1    t1, $f22
-       mtc1    t1, $f23
-       mtc1    t1, $f24
-       mtc1    t1, $f25
-       mtc1    t1, $f26
-       mtc1    t1, $f27
-       mtc1    t1, $f28
-       mtc1    t1, $f29
-       mtc1    t1, $f30
-       mtc1    t1, $f31
-
-#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6)
-       .set    push
-       .set    MIPS_ISA_LEVEL_RAW
-       .set    fp=64
-       sll     t0, t0, 5                       # is Status.FR set?
-       bgez    t0, 1f                          # no: skip setting upper 32b
-
-       mthc1   t1, $f0
-       mthc1   t1, $f1
-       mthc1   t1, $f2
-       mthc1   t1, $f3
-       mthc1   t1, $f4
-       mthc1   t1, $f5
-       mthc1   t1, $f6
-       mthc1   t1, $f7
-       mthc1   t1, $f8
-       mthc1   t1, $f9
-       mthc1   t1, $f10
-       mthc1   t1, $f11
-       mthc1   t1, $f12
-       mthc1   t1, $f13
-       mthc1   t1, $f14
-       mthc1   t1, $f15
-       mthc1   t1, $f16
-       mthc1   t1, $f17
-       mthc1   t1, $f18
-       mthc1   t1, $f19
-       mthc1   t1, $f20
-       mthc1   t1, $f21
-       mthc1   t1, $f22
-       mthc1   t1, $f23
-       mthc1   t1, $f24
-       mthc1   t1, $f25
-       mthc1   t1, $f26
-       mthc1   t1, $f27
-       mthc1   t1, $f28
-       mthc1   t1, $f29
-       mthc1   t1, $f30
-       mthc1   t1, $f31
-1:     .set    pop
-#endif /* CONFIG_CPU_MIPS32_R2 || CONFIG_CPU_MIPS32_R6 */
-#else
-       .set    MIPS_ISA_ARCH_LEVEL_RAW
-       dmtc1   t1, $f0
-       dmtc1   t1, $f2
-       dmtc1   t1, $f4
-       dmtc1   t1, $f6
-       dmtc1   t1, $f8
-       dmtc1   t1, $f10
-       dmtc1   t1, $f12
-       dmtc1   t1, $f14
-       dmtc1   t1, $f16
-       dmtc1   t1, $f18
-       dmtc1   t1, $f20
-       dmtc1   t1, $f22
-       dmtc1   t1, $f24
-       dmtc1   t1, $f26
-       dmtc1   t1, $f28
-       dmtc1   t1, $f30
-#endif
-       jr      ra
-       END(_init_fpu)
-
-       .set pop        /* SET_HARDFLOAT */
-
        .set    noreorder
 
 /**