Merge branch 'for-next' of git://git.samba.org/sfrench/cifs-2.6

[sfrench/cifs-2.6.git] / arch / mips / kernel / mips-r2-to-r6-emul.c

diff --git a/arch/mips/kernel/mips-r2-to-r6-emul.c b/arch/mips/kernel/mips-r2-to-r6-emul.c
index 550e7d03090a18fc9cafd8d2ed77ffd89d927a3d..ae64c8f56a8c788450876bd368bc6dba8cab54a7 100644 (file)
--- a/arch/mips/kernel/mips-r2-to-r6-emul.c
+++ b/arch/mips/kernel/mips-r2-to-r6-emul.c
@@ -1096,10 +1096,20 @@ repeat:
                }
                break;
 
-       case beql_op:
-       case bnel_op:
        case blezl_op:
        case bgtzl_op:
+               /*
+                * For BLEZL and BGTZL, rt field must be set to 0. If this
+                * is not the case, this may be an encoding of a MIPS R6
+                * instruction, so return to CPU execution if this occurs
+                */
+               if (MIPSInst_RT(inst)) {
+                       err = SIGILL;
+                       break;
+               }
+               /* fall through */
+       case beql_op:
+       case bnel_op:
                if (delay_slot(regs)) {
                        err = SIGILL;
                        break;
@@ -2329,6 +2339,8 @@ static int mipsr2_stats_clear_show(struct seq_file *s, void *unused)
        __this_cpu_write((mipsr2bremustats).bgezl, 0);
        __this_cpu_write((mipsr2bremustats).bltzll, 0);
        __this_cpu_write((mipsr2bremustats).bgezll, 0);
+       __this_cpu_write((mipsr2bremustats).bltzall, 0);
+       __this_cpu_write((mipsr2bremustats).bgezall, 0);
        __this_cpu_write((mipsr2bremustats).bltzal, 0);
        __this_cpu_write((mipsr2bremustats).bgezal, 0);
        __this_cpu_write((mipsr2bremustats).beql, 0);