Merge branch 'virtex-for-2.6.25' of git://git.secretlab.ca/git/linux-2.6-virtex into...

[sfrench/cifs-2.6.git] / arch / ia64 / kernel / patch.c

diff --git a/arch/ia64/kernel/patch.c b/arch/ia64/kernel/patch.c
index 6a4ac7d70b357e34901faec54e77009d9d9cd505..2cb9425e04210fed5de6e6168074f04193210971 100644 (file)
--- a/arch/ia64/kernel/patch.c
+++ b/arch/ia64/kernel/patch.c
@@ -115,7 +115,7 @@ ia64_patch_vtop (unsigned long start, unsigned long end)
        ia64_srlz_i();
 }
 
-void
+void __init
 ia64_patch_mckinley_e9 (unsigned long start, unsigned long end)
 {
        static int first_time = 1;
@@ -129,9 +129,6 @@ ia64_patch_mckinley_e9 (unsigned long start, unsigned long end)
                first_time = 0;
                if (need_workaround)
                        printk(KERN_INFO "Leaving McKinley Errata 9 workaround enabled\n");
-               else
-                       printk(KERN_INFO "McKinley Errata 9 workaround not needed; "
-                              "disabling it\n");
        }
        if (need_workaround)
                return;
@@ -149,7 +146,7 @@ ia64_patch_mckinley_e9 (unsigned long start, unsigned long end)
        ia64_srlz_i();
 }
 
-static void
+static void __init
 patch_fsyscall_table (unsigned long start, unsigned long end)
 {
        extern unsigned long fsyscall_table[NR_syscalls];
@@ -166,7 +163,7 @@ patch_fsyscall_table (unsigned long start, unsigned long end)
        ia64_srlz_i();
 }
 
-static void
+static void __init
 patch_brl_fsys_bubble_down (unsigned long start, unsigned long end)
 {
        extern char fsys_bubble_down[];
@@ -184,7 +181,7 @@ patch_brl_fsys_bubble_down (unsigned long start, unsigned long end)
        ia64_srlz_i();
 }
 
-void
+void __init
 ia64_patch_gate (void)
 {
 #      define START(name)      ((unsigned long) __start_gate_##name##_patchlist)
@@ -195,3 +192,23 @@ ia64_patch_gate (void)
        ia64_patch_vtop(START(vtop), END(vtop));
        ia64_patch_mckinley_e9(START(mckinley_e9), END(mckinley_e9));
 }
+
+void ia64_patch_phys_stack_reg(unsigned long val)
+{
+       s32 * offp = (s32 *) __start___phys_stack_reg_patchlist;
+       s32 * end = (s32 *) __end___phys_stack_reg_patchlist;
+       u64 ip, mask, imm;
+
+       /* see instruction format A4: adds r1 = imm13, r3 */
+       mask = (0x3fUL << 27) | (0x7f << 13);
+       imm = (((val >> 7) & 0x3f) << 27) | (val & 0x7f) << 13;
+
+       while (offp < end) {
+               ip = (u64) offp + *offp;
+               ia64_patch(ip, mask, imm);
+               ia64_fc(ip);
+               ++offp;
+       }
+       ia64_sync_i();
+       ia64_srlz_i();
+}