[IA64] Support multiple CPUs going through OS_MCA

[sfrench/cifs-2.6.git] / arch / ia64 / kernel / mca_asm.S

diff --git a/arch/ia64/kernel/mca_asm.S b/arch/ia64/kernel/mca_asm.S
index 6dff024cd62b03f45ae9f00cde9ae9c1a0fcebc8..0f5965fcdf85133fbf0c455f714dcbea091eea2d 100644 (file)
--- a/arch/ia64/kernel/mca_asm.S
+++ b/arch/ia64/kernel/mca_asm.S
@@ -19,7 +19,6 @@
 // 12/08/05 Keith Owens <kaos@sgi.com>
 //                Use per cpu MCA/INIT stacks for all data.
 //
-#include <linux/config.h>
 #include <linux/threads.h>
 
 #include <asm/asmmacro.h>
@@ -102,14 +101,6 @@ ia64_do_tlb_purge:
        ;;
        srlz.d
        ;;
-       // 2. Purge DTR for PERCPU data.
-       movl r16=PERCPU_ADDR
-       mov r18=PERCPU_PAGE_SHIFT<<2
-       ;;
-       ptr.d r16,r18
-       ;;
-       srlz.d
-       ;;
        // 3. Purge ITR for PAL code.
        GET_THIS_PADDR(r2, ia64_mca_pal_base)
        ;;
@@ -142,14 +133,6 @@ ia64_do_tlb_purge:
 //StartMain////////////////////////////////////////////////////////////////////
 
 ia64_os_mca_dispatch:
-       // Serialize all MCA processing
-       mov     r3=1;;
-       LOAD_PHYSICAL(p0,r2,ia64_mca_serialize);;
-ia64_os_mca_spin:
-       xchg4   r4=[r2],r3;;
-       cmp.ne  p6,p0=r4,r0
-(p6)   br ia64_os_mca_spin
-
        mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET    // use the MCA stack
        LOAD_PHYSICAL(p0,r2,1f)                 // return address
        mov r19=1                               // All MCA events are treated as monarch (for now)
@@ -159,7 +142,7 @@ ia64_os_mca_spin:
        GET_IA64_MCA_DATA(r2)
        // Using MCA stack, struct ia64_sal_os_state, variable proc_state_param
        ;;
-       add r3=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SOS_OFFSET+IA64_SAL_OS_STATE_PROC_STATE_PARAM_OFFSET, r2
+       add r3=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SOS_OFFSET+SOS(PROC_STATE_PARAM), r2
        ;;
        ld8 r18=[r3]                            // Get processor state parameter on existing PALE_CHECK.
        ;;
@@ -197,22 +180,6 @@ ia64_reload_tr:
        srlz.i
        srlz.d
        ;;
-       // 2. Reload DTR register for PERCPU data.
-       GET_THIS_PADDR(r2, ia64_mca_per_cpu_pte)
-       ;;
-       movl r16=PERCPU_ADDR            // vaddr
-       movl r18=PERCPU_PAGE_SHIFT<<2
-       ;;
-       mov cr.itir=r18
-       mov cr.ifa=r16
-       ;;
-       ld8 r18=[r2]                    // load per-CPU PTE
-       mov r16=IA64_TR_PERCPU_DATA;
-       ;;
-       itr.d dtr[r16]=r18
-       ;;
-       srlz.d
-       ;;
        // 3. Reload ITR for PAL code.
        GET_THIS_PADDR(r2, ia64_mca_pal_pte)
        ;;
@@ -316,10 +283,6 @@ END(ia64_os_mca_virtual_begin)
 
        mov             b0=r12                  // SAL_CHECK return address
 
-       // release lock
-       LOAD_PHYSICAL(p0,r3,ia64_mca_serialize);;
-       st4.rel         [r3]=r0
-
        br              b0
 
 //EndMain//////////////////////////////////////////////////////////////////////
@@ -479,9 +442,11 @@ ia64_state_save:
        st8 [temp2]=r11,16      // rv_rc
        mov r11=cr.iipa
        ;;
-       st8 [temp1]=r18,16      // proc_state_param
-       st8 [temp2]=r19,16      // monarch
+       st8 [temp1]=r18         // proc_state_param
+       st8 [temp2]=r19         // monarch
        mov r6=IA64_KR(CURRENT)
+       add temp1=SOS(SAL_RA), regs
+       add temp2=SOS(SAL_GP), regs
        ;;
        st8 [temp1]=r12,16      // sal_ra
        st8 [temp2]=r10,16      // sal_gp
@@ -503,12 +468,14 @@ ia64_state_save:
        st8 [temp2]=r11,16      // cr.iipa
        mov r12=cr.iim
        ;;
-       st8 [temp1]=r12,16      // cr.iim
+       st8 [temp1]=r12         // cr.iim
 (p1)   mov r12=IA64_MCA_COLD_BOOT
 (p2)   mov r12=IA64_INIT_WARM_BOOT
        mov r6=cr.iha
+       add temp1=SOS(OS_STATUS), regs
        ;;
-       st8 [temp2]=r6,16       // cr.iha
+       st8 [temp2]=r6          // cr.iha
+       add temp2=SOS(CONTEXT), regs
        st8 [temp1]=r12         // os_status, default is cold boot
        mov r6=IA64_MCA_SAME_CONTEXT
        ;;
@@ -820,8 +787,8 @@ ia64_state_restore:
        // Restore the SAL to OS state. The previous code left regs at pt_regs.
        add regs=MCA_SOS_OFFSET-MCA_PT_REGS_OFFSET, regs
        ;;
-       add temp1=IA64_SAL_OS_STATE_COMMON_OFFSET, regs
-       add temp2=IA64_SAL_OS_STATE_COMMON_OFFSET+8, regs
+       add temp1=SOS(SAL_RA), regs
+       add temp2=SOS(SAL_GP), regs
        ;;
        ld8 r12=[temp1],16      // sal_ra
        ld8 r9=[temp2],16       // sal_gp
@@ -842,8 +809,10 @@ ia64_state_restore:
        ;;
        mov cr.itir=temp3
        mov cr.iipa=temp4
-       ld8 temp3=[temp1],16    // cr.iim
-       ld8 temp4=[temp2],16    // cr.iha
+       ld8 temp3=[temp1]       // cr.iim
+       ld8 temp4=[temp2]               // cr.iha
+       add temp1=SOS(OS_STATUS), regs
+       add temp2=SOS(CONTEXT), regs
        ;;
        mov cr.iim=temp3
        mov cr.iha=temp4
@@ -916,7 +885,7 @@ ia64_state_restore:
 
 ia64_new_stack:
        add regs=MCA_PT_REGS_OFFSET, r3
-       add temp2=MCA_SOS_OFFSET+IA64_SAL_OS_STATE_PAL_MIN_STATE_OFFSET, r3
+       add temp2=MCA_SOS_OFFSET+SOS(PAL_MIN_STATE), r3
        mov b0=r2                       // save return address
        GET_IA64_MCA_DATA(temp1)
        invala
@@ -1020,18 +989,13 @@ ia64_old_stack:
 
 ia64_set_kernel_registers:
        add temp3=MCA_SP_OFFSET, r3
-       add temp4=MCA_SOS_OFFSET+IA64_SAL_OS_STATE_OS_GP_OFFSET, r3
        mov b0=r2               // save return address
        GET_IA64_MCA_DATA(temp1)
        ;;
-       add temp4=temp4, temp1  // &struct ia64_sal_os_state.os_gp
        add r12=temp1, temp3    // kernel stack pointer on MCA/INIT stack
        add r13=temp1, r3       // set current to start of MCA/INIT stack
        add r20=temp1, r3       // physical start of MCA/INIT stack
        ;;
-       ld8 r1=[temp4]          // OS GP from SAL OS state
-       ;;
-       DATA_PA_TO_VA(r1,temp1)
        DATA_PA_TO_VA(r12,temp2)
        DATA_PA_TO_VA(r13,temp3)
        ;;
@@ -1062,6 +1026,10 @@ ia64_set_kernel_registers:
        mov cr.itir=r18
        mov cr.ifa=r13
        mov r20=IA64_TR_CURRENT_STACK
+
+       movl r17=FPSR_DEFAULT
+       ;;
+       mov.m ar.fpsr=r17                       // set ar.fpsr to kernel default value
        ;;
        itr.d dtr[r20]=r21
        ;;