Merge branch 'for-linus' of git://git.infradead.org/~dedekind/ubi-2.6

[sfrench/cifs-2.6.git] / arch / blackfin / mach-common / dpmc.S

diff --git a/arch/blackfin/mach-common/dpmc.S b/arch/blackfin/mach-common/dpmc.S
index b82c096e1980de0749c6a76b5a18f6ab17fb7f4f..9d45aa3265b19a399e403045c1cda8ad3cac5130 100644 (file)
--- a/arch/blackfin/mach-common/dpmc.S
+++ b/arch/blackfin/mach-common/dpmc.S
@@ -31,140 +31,6 @@
 #include <asm/blackfin.h>
 #include <asm/mach/irq.h>
 
-.text
-
-ENTRY(_unmask_wdog_wakeup_evt)
-       [--SP] = ( R7:0, P5:0 );
-#if defined(CONFIG_BF561)
-       P0.H = hi(SICA_IWR1);
-       P0.L = lo(SICA_IWR1);
-#elif defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
-       P0.h = HI(SIC_IWR0);
-       P0.l = LO(SIC_IWR0);
-#else
-       P0.h = HI(SIC_IWR);
-       P0.l = LO(SIC_IWR);
-#endif
-       R7 = [P0];
-#if defined(CONFIG_BF561)
-       BITSET(R7, 27);
-#else
-       BITSET(R7,(IRQ_WATCH - IVG7));
-#endif
-       [P0] = R7;
-       SSYNC;
-
-       ( R7:0, P5:0 ) = [SP++];
-       RTS;
-
-.LWRITE_TO_STAT:
-       /* When watch dog timer is enabled, a write to STAT will load the
-        * contents of CNT to STAT
-        */
-       R7 = 0x0000(z);
-#if defined(CONFIG_BF561)
-       P0.h = HI(WDOGA_STAT);
-       P0.l = LO(WDOGA_STAT);
-#else
-       P0.h = HI(WDOG_STAT);
-       P0.l = LO(WDOG_STAT);
-#endif
-       [P0] = R7;
-       SSYNC;
-       JUMP .LSKIP_WRITE_TO_STAT;
-
-ENTRY(_program_wdog_timer)
-       [--SP] = ( R7:0, P5:0 );
-#if defined(CONFIG_BF561)
-       P0.h = HI(WDOGA_CNT);
-       P0.l = LO(WDOGA_CNT);
-#else
-       P0.h = HI(WDOG_CNT);
-       P0.l = LO(WDOG_CNT);
-#endif
-       [P0] = R0;
-       SSYNC;
-
-#if defined(CONFIG_BF561)
-       P0.h = HI(WDOGA_CTL);
-       P0.l = LO(WDOGA_CTL);
-#else
-       P0.h = HI(WDOG_CTL);
-       P0.l = LO(WDOG_CTL);
-#endif
-       R7 = W[P0](Z);
-       CC = BITTST(R7,1);
-       if !CC JUMP .LWRITE_TO_STAT;
-       CC = BITTST(R7,2);
-       if !CC JUMP .LWRITE_TO_STAT;
-
-.LSKIP_WRITE_TO_STAT:
-#if defined(CONFIG_BF561)
-       P0.h = HI(WDOGA_CTL);
-       P0.l = LO(WDOGA_CTL);
-#else
-       P0.h = HI(WDOG_CTL);
-       P0.l = LO(WDOG_CTL);
-#endif
-       R7 = W[P0](Z);
-       BITCLR(R7,1);   /* Enable GP event */
-       BITSET(R7,2);
-       W[P0] = R7.L;
-       SSYNC;
-       NOP;
-
-       R7 = W[P0](Z);
-       BITCLR(R7,4);   /* Enable the wdog counter */
-       W[P0] = R7.L;
-       SSYNC;
-
-       ( R7:0, P5:0 ) = [SP++];
-       RTS;
-
-ENTRY(_clear_wdog_wakeup_evt)
-       [--SP] = ( R7:0, P5:0 );
-
-#if defined(CONFIG_BF561)
-       P0.h = HI(WDOGA_CTL);
-       P0.l = LO(WDOGA_CTL);
-#else
-       P0.h = HI(WDOG_CTL);
-       P0.l = LO(WDOG_CTL);
-#endif
-       R7 = 0x0AD6(Z);
-       W[P0] = R7.L;
-       SSYNC;
-
-       R7 = W[P0](Z);
-       BITSET(R7,15);
-       W[P0] = R7.L;
-       SSYNC;
-
-       R7 = W[P0](Z);
-       BITSET(R7,1);
-       BITSET(R7,2);
-       W[P0] = R7.L;
-       SSYNC;
-
-       ( R7:0, P5:0 ) = [SP++];
-       RTS;
-
-ENTRY(_disable_wdog_timer)
-       [--SP] = ( R7:0, P5:0 );
-#if defined(CONFIG_BF561)
-       P0.h = HI(WDOGA_CTL);
-       P0.l = LO(WDOGA_CTL);
-#else
-       P0.h = HI(WDOG_CTL);
-       P0.l = LO(WDOG_CTL);
-#endif
-       R7 = 0xAD6(Z);
-       W[P0] = R7.L;
-       SSYNC;
-       ( R7:0, P5:0 ) = [SP++];
-       RTS;
-
-#if !defined(CONFIG_BF561)
 
 .section .l1.text
 
@@ -191,6 +57,9 @@ ENTRY(_sleep_mode)
        call _test_pll_locked;
 
        R0 = IWR_ENABLE(0);
+       R1 = IWR_DISABLE_ALL;
+       R2 = IWR_DISABLE_ALL;
+
        call _set_sic_iwr;
 
        P0.H = hi(PLL_CTL);
@@ -237,6 +106,10 @@ ENTRY(_deep_sleep)
 
        CLI R4;
 
+       R0 = IWR_ENABLE(0);
+       R1 = IWR_DISABLE_ALL;
+       R2 = IWR_DISABLE_ALL;
+
        call _set_sic_iwr;
 
        call _set_dram_srfs;
@@ -261,6 +134,9 @@ ENTRY(_deep_sleep)
        call _test_pll_locked;
 
        R0 = IWR_ENABLE(0);
+       R1 = IWR_DISABLE_ALL;
+       R2 = IWR_DISABLE_ALL;
+
        call _set_sic_iwr;
 
        P0.H = hi(PLL_CTL);
@@ -286,7 +162,13 @@ ENTRY(_sleep_deeper)
        CLI R4;
 
        P3 = R0;
+       P4 = R1;
+       P5 = R2;
+
        R0 = IWR_ENABLE(0);
+       R1 = IWR_DISABLE_ALL;
+       R2 = IWR_DISABLE_ALL;
+
        call _set_sic_iwr;
        call _set_dram_srfs;    /* Set SDRAM Self Refresh */
 
@@ -327,6 +209,8 @@ ENTRY(_sleep_deeper)
        call _test_pll_locked;
 
        R0 = P3;
+       R1 = P4;
+       R3 = P5;
        call _set_sic_iwr;      /* Set Awake from IDLE */
 
        P0.H = hi(PLL_CTL);
@@ -340,6 +224,9 @@ ENTRY(_sleep_deeper)
        call _test_pll_locked;
 
        R0 = IWR_ENABLE(0);
+       R1 = IWR_DISABLE_ALL;
+       R2 = IWR_DISABLE_ALL;
+
        call _set_sic_iwr;      /* Set Awake from IDLE PLL */
 
        P0.H = hi(VR_CTL);
@@ -417,22 +304,33 @@ ENTRY(_unset_dram_srfs)
        RTS;
 
 ENTRY(_set_sic_iwr)
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561)
        P0.H = hi(SIC_IWR0);
        P0.L = lo(SIC_IWR0);
+       P1.H = hi(SIC_IWR1);
+       P1.L = lo(SIC_IWR1);
+       [P1] = R1;
+#if defined(CONFIG_BF54x)
+       P1.H = hi(SIC_IWR2);
+       P1.L = lo(SIC_IWR2);
+       [P1] = R2;
+#endif
 #else
        P0.H = hi(SIC_IWR);
        P0.L = lo(SIC_IWR);
 #endif
        [P0] = R0;
+
        SSYNC;
        RTS;
 
 ENTRY(_set_rtc_istat)
+#ifndef CONFIG_BF561
        P0.H = hi(RTC_ISTAT);
        P0.L = lo(RTC_ISTAT);
        w[P0] = R0.L;
        SSYNC;
+#endif
        RTS;
 
 ENTRY(_test_pll_locked)
@@ -443,4 +341,3 @@ ENTRY(_test_pll_locked)
        CC = BITTST(R0,5);
        IF !CC JUMP 1b;
        RTS;
-#endif