Merge branch 'for-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu

[sfrench/cifs-2.6.git] / arch / arm64 / include / asm / sysreg.h

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 262ae18f0e055a009dccdd6f1eaf7e05c068572d..0e1960c59197aa581c4c0e1ee4fb1f5558f902f6 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -20,6 +20,7 @@
 #ifndef __ASM_SYSREG_H
 #define __ASM_SYSREG_H
 
+#include <asm/compiler.h>
 #include <linux/stringify.h>
 
 /*
@@ -175,6 +176,16 @@
 #define SYS_AFSR0_EL1                  sys_reg(3, 0, 5, 1, 0)
 #define SYS_AFSR1_EL1                  sys_reg(3, 0, 5, 1, 1)
 #define SYS_ESR_EL1                    sys_reg(3, 0, 5, 2, 0)
+
+#define SYS_ERRIDR_EL1                 sys_reg(3, 0, 5, 3, 0)
+#define SYS_ERRSELR_EL1                        sys_reg(3, 0, 5, 3, 1)
+#define SYS_ERXFR_EL1                  sys_reg(3, 0, 5, 4, 0)
+#define SYS_ERXCTLR_EL1                        sys_reg(3, 0, 5, 4, 1)
+#define SYS_ERXSTATUS_EL1              sys_reg(3, 0, 5, 4, 2)
+#define SYS_ERXADDR_EL1                        sys_reg(3, 0, 5, 4, 3)
+#define SYS_ERXMISC0_EL1               sys_reg(3, 0, 5, 5, 0)
+#define SYS_ERXMISC1_EL1               sys_reg(3, 0, 5, 5, 1)
+
 #define SYS_FAR_EL1                    sys_reg(3, 0, 6, 0, 0)
 #define SYS_PAR_EL1                    sys_reg(3, 0, 7, 4, 0)
 
@@ -278,6 +289,7 @@
 #define SYS_AMAIR_EL1                  sys_reg(3, 0, 10, 3, 0)
 
 #define SYS_VBAR_EL1                   sys_reg(3, 0, 12, 0, 0)
+#define SYS_DISR_EL1                   sys_reg(3, 0, 12, 1, 1)
 
 #define SYS_ICC_IAR0_EL1               sys_reg(3, 0, 12, 8, 0)
 #define SYS_ICC_EOIR0_EL1              sys_reg(3, 0, 12, 8, 1)
@@ -353,8 +365,10 @@
 
 #define SYS_DACR32_EL2                 sys_reg(3, 4, 3, 0, 0)
 #define SYS_IFSR32_EL2                 sys_reg(3, 4, 5, 0, 1)
+#define SYS_VSESR_EL2                  sys_reg(3, 4, 5, 2, 3)
 #define SYS_FPEXC32_EL2                        sys_reg(3, 4, 5, 3, 0)
 
+#define SYS_VDISR_EL2                  sys_reg(3, 4, 12, 1,  1)
 #define __SYS__AP0Rx_EL2(x)            sys_reg(3, 4, 12, 8, x)
 #define SYS_ICH_AP0R0_EL2              __SYS__AP0Rx_EL2(0)
 #define SYS_ICH_AP0R1_EL2              __SYS__AP0Rx_EL2(1)
@@ -398,25 +412,82 @@
 
 /* Common SCTLR_ELx flags. */
 #define SCTLR_ELx_EE    (1 << 25)
+#define SCTLR_ELx_IESB (1 << 21)
+#define SCTLR_ELx_WXN  (1 << 19)
 #define SCTLR_ELx_I    (1 << 12)
 #define SCTLR_ELx_SA   (1 << 3)
 #define SCTLR_ELx_C    (1 << 2)
 #define SCTLR_ELx_A    (1 << 1)
 #define SCTLR_ELx_M    1
 
+#define SCTLR_ELx_FLAGS        (SCTLR_ELx_M  | SCTLR_ELx_A | SCTLR_ELx_C | \
+                        SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB)
+
+/* SCTLR_EL2 specific flags. */
 #define SCTLR_EL2_RES1 ((1 << 4)  | (1 << 5)  | (1 << 11) | (1 << 16) | \
                         (1 << 18) | (1 << 22) | (1 << 23) | (1 << 28) | \
                         (1 << 29))
+#define SCTLR_EL2_RES0 ((1 << 6)  | (1 << 7)  | (1 << 8)  | (1 << 9)  | \
+                        (1 << 10) | (1 << 13) | (1 << 14) | (1 << 15) | \
+                        (1 << 17) | (1 << 20) | (1 << 24) | (1 << 26) | \
+                        (1 << 27) | (1 << 30) | (1 << 31))
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define ENDIAN_SET_EL2         SCTLR_ELx_EE
+#define ENDIAN_CLEAR_EL2       0
+#else
+#define ENDIAN_SET_EL2         0
+#define ENDIAN_CLEAR_EL2       SCTLR_ELx_EE
+#endif
+
+/* SCTLR_EL2 value used for the hyp-stub */
+#define SCTLR_EL2_SET  (SCTLR_ELx_IESB   | ENDIAN_SET_EL2   | SCTLR_EL2_RES1)
+#define SCTLR_EL2_CLEAR        (SCTLR_ELx_M      | SCTLR_ELx_A    | SCTLR_ELx_C   | \
+                        SCTLR_ELx_SA     | SCTLR_ELx_I    | SCTLR_ELx_WXN | \
+                        ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0)
+
+/* Check all the bits are accounted for */
+#define SCTLR_EL2_BUILD_BUG_ON_MISSING_BITS    BUILD_BUG_ON((SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != ~0)
 
-#define SCTLR_ELx_FLAGS        (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
-                        SCTLR_ELx_SA | SCTLR_ELx_I)
 
 /* SCTLR_EL1 specific flags. */
 #define SCTLR_EL1_UCI          (1 << 26)
+#define SCTLR_EL1_E0E          (1 << 24)
 #define SCTLR_EL1_SPAN         (1 << 23)
+#define SCTLR_EL1_NTWE         (1 << 18)
+#define SCTLR_EL1_NTWI         (1 << 16)
 #define SCTLR_EL1_UCT          (1 << 15)
+#define SCTLR_EL1_DZE          (1 << 14)
+#define SCTLR_EL1_UMA          (1 << 9)
 #define SCTLR_EL1_SED          (1 << 8)
+#define SCTLR_EL1_ITD          (1 << 7)
 #define SCTLR_EL1_CP15BEN      (1 << 5)
+#define SCTLR_EL1_SA0          (1 << 4)
+
+#define SCTLR_EL1_RES1 ((1 << 11) | (1 << 20) | (1 << 22) | (1 << 28) | \
+                        (1 << 29))
+#define SCTLR_EL1_RES0  ((1 << 6)  | (1 << 10) | (1 << 13) | (1 << 17) | \
+                        (1 << 27) | (1 << 30) | (1 << 31))
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define ENDIAN_SET_EL1         (SCTLR_EL1_E0E | SCTLR_ELx_EE)
+#define ENDIAN_CLEAR_EL1       0
+#else
+#define ENDIAN_SET_EL1         0
+#define ENDIAN_CLEAR_EL1       (SCTLR_EL1_E0E | SCTLR_ELx_EE)
+#endif
+
+#define SCTLR_EL1_SET  (SCTLR_ELx_M    | SCTLR_ELx_C    | SCTLR_ELx_SA   |\
+                        SCTLR_EL1_SA0  | SCTLR_EL1_SED  | SCTLR_ELx_I    |\
+                        SCTLR_EL1_DZE  | SCTLR_EL1_UCT  | SCTLR_EL1_NTWI |\
+                        SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\
+                        ENDIAN_SET_EL1 | SCTLR_EL1_UCI  | SCTLR_EL1_RES1)
+#define SCTLR_EL1_CLEAR        (SCTLR_ELx_A   | SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD    |\
+                        SCTLR_EL1_UMA | SCTLR_ELx_WXN     | ENDIAN_CLEAR_EL1 |\
+                        SCTLR_EL1_RES0)
+
+/* Check all the bits are accounted for */
+#define SCTLR_EL1_BUILD_BUG_ON_MISSING_BITS    BUILD_BUG_ON((SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != ~0)
 
 /* id_aa64isar0 */
 #define ID_AA64ISAR0_FHM_SHIFT         48
@@ -439,7 +510,9 @@
 
 /* id_aa64pfr0 */
 #define ID_AA64PFR0_CSV3_SHIFT         60
+#define ID_AA64PFR0_CSV2_SHIFT         56
 #define ID_AA64PFR0_SVE_SHIFT          32
+#define ID_AA64PFR0_RAS_SHIFT          28
 #define ID_AA64PFR0_GIC_SHIFT          24
 #define ID_AA64PFR0_ASIMD_SHIFT                20
 #define ID_AA64PFR0_FP_SHIFT           16
@@ -449,6 +522,7 @@
 #define ID_AA64PFR0_EL0_SHIFT          0
 
 #define ID_AA64PFR0_SVE                        0x1
+#define ID_AA64PFR0_RAS_V1             0x1
 #define ID_AA64PFR0_FP_NI              0xf
 #define ID_AA64PFR0_FP_SUPPORTED       0x0
 #define ID_AA64PFR0_ASIMD_NI           0xf
@@ -592,6 +666,7 @@
 
 #else
 
+#include <linux/build_bug.h>
 #include <linux/types.h>
 
 asm(
@@ -648,6 +723,9 @@ static inline void config_sctlr_el1(u32 clear, u32 set)
 {
        u32 val;
 
+       SCTLR_EL2_BUILD_BUG_ON_MISSING_BITS;
+       SCTLR_EL1_BUILD_BUG_ON_MISSING_BITS;
+
        val = read_sysreg(sctlr_el1);
        val &= ~clear;
        val |= set;