Merge tag 'fscrypt_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso...

[sfrench/cifs-2.6.git] / arch / arm64 / include / asm / arch_gicv3.h

diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index f37e3a21f6e767cb16d473b46ebe7ca487a47fb4..1a98bc8602a2aa8216716468391eb0575371a954 100644 (file)
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -20,69 +20,14 @@
 
 #include <asm/sysreg.h>
 
-#define ICC_EOIR1_EL1                  sys_reg(3, 0, 12, 12, 1)
-#define ICC_DIR_EL1                    sys_reg(3, 0, 12, 11, 1)
-#define ICC_IAR1_EL1                   sys_reg(3, 0, 12, 12, 0)
-#define ICC_SGI1R_EL1                  sys_reg(3, 0, 12, 11, 5)
-#define ICC_PMR_EL1                    sys_reg(3, 0, 4, 6, 0)
-#define ICC_CTLR_EL1                   sys_reg(3, 0, 12, 12, 4)
-#define ICC_SRE_EL1                    sys_reg(3, 0, 12, 12, 5)
-#define ICC_GRPEN1_EL1                 sys_reg(3, 0, 12, 12, 7)
-#define ICC_BPR1_EL1                   sys_reg(3, 0, 12, 12, 3)
-
-#define ICC_SRE_EL2                    sys_reg(3, 4, 12, 9, 5)
-
-/*
- * System register definitions
- */
-#define ICH_VSEIR_EL2                  sys_reg(3, 4, 12, 9, 4)
-#define ICH_HCR_EL2                    sys_reg(3, 4, 12, 11, 0)
-#define ICH_VTR_EL2                    sys_reg(3, 4, 12, 11, 1)
-#define ICH_MISR_EL2                   sys_reg(3, 4, 12, 11, 2)
-#define ICH_EISR_EL2                   sys_reg(3, 4, 12, 11, 3)
-#define ICH_ELSR_EL2                   sys_reg(3, 4, 12, 11, 5)
-#define ICH_VMCR_EL2                   sys_reg(3, 4, 12, 11, 7)
-
-#define __LR0_EL2(x)                   sys_reg(3, 4, 12, 12, x)
-#define __LR8_EL2(x)                   sys_reg(3, 4, 12, 13, x)
-
-#define ICH_LR0_EL2                    __LR0_EL2(0)
-#define ICH_LR1_EL2                    __LR0_EL2(1)
-#define ICH_LR2_EL2                    __LR0_EL2(2)
-#define ICH_LR3_EL2                    __LR0_EL2(3)
-#define ICH_LR4_EL2                    __LR0_EL2(4)
-#define ICH_LR5_EL2                    __LR0_EL2(5)
-#define ICH_LR6_EL2                    __LR0_EL2(6)
-#define ICH_LR7_EL2                    __LR0_EL2(7)
-#define ICH_LR8_EL2                    __LR8_EL2(0)
-#define ICH_LR9_EL2                    __LR8_EL2(1)
-#define ICH_LR10_EL2                   __LR8_EL2(2)
-#define ICH_LR11_EL2                   __LR8_EL2(3)
-#define ICH_LR12_EL2                   __LR8_EL2(4)
-#define ICH_LR13_EL2                   __LR8_EL2(5)
-#define ICH_LR14_EL2                   __LR8_EL2(6)
-#define ICH_LR15_EL2                   __LR8_EL2(7)
-
-#define __AP0Rx_EL2(x)                 sys_reg(3, 4, 12, 8, x)
-#define ICH_AP0R0_EL2                  __AP0Rx_EL2(0)
-#define ICH_AP0R1_EL2                  __AP0Rx_EL2(1)
-#define ICH_AP0R2_EL2                  __AP0Rx_EL2(2)
-#define ICH_AP0R3_EL2                  __AP0Rx_EL2(3)
-
-#define __AP1Rx_EL2(x)                 sys_reg(3, 4, 12, 9, x)
-#define ICH_AP1R0_EL2                  __AP1Rx_EL2(0)
-#define ICH_AP1R1_EL2                  __AP1Rx_EL2(1)
-#define ICH_AP1R2_EL2                  __AP1Rx_EL2(2)
-#define ICH_AP1R3_EL2                  __AP1Rx_EL2(3)
-
 #ifndef __ASSEMBLY__
 
 #include <linux/stringify.h>
 #include <asm/barrier.h>
 #include <asm/cacheflush.h>
 
-#define read_gicreg                    read_sysreg_s
-#define write_gicreg                   write_sysreg_s
+#define read_gicreg(r)                 read_sysreg_s(SYS_ ## r)
+#define write_gicreg(v, r)             write_sysreg_s(v, SYS_ ## r)
 
 /*
  * Low-level accessors
@@ -93,13 +38,13 @@
 
 static inline void gic_write_eoir(u32 irq)
 {
-       write_sysreg_s(irq, ICC_EOIR1_EL1);
+       write_sysreg_s(irq, SYS_ICC_EOIR1_EL1);
        isb();
 }
 
 static inline void gic_write_dir(u32 irq)
 {
-       write_sysreg_s(irq, ICC_DIR_EL1);
+       write_sysreg_s(irq, SYS_ICC_DIR_EL1);
        isb();
 }
 
@@ -107,7 +52,7 @@ static inline u64 gic_read_iar_common(void)
 {
        u64 irqstat;
 
-       irqstat = read_sysreg_s(ICC_IAR1_EL1);
+       irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
        dsb(sy);
        return irqstat;
 }
@@ -124,7 +69,7 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
        u64 irqstat;
 
        nops(8);
-       irqstat = read_sysreg_s(ICC_IAR1_EL1);
+       irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
        nops(4);
        mb();
 
@@ -133,40 +78,40 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
 
 static inline void gic_write_pmr(u32 val)
 {
-       write_sysreg_s(val, ICC_PMR_EL1);
+       write_sysreg_s(val, SYS_ICC_PMR_EL1);
 }
 
 static inline void gic_write_ctlr(u32 val)
 {
-       write_sysreg_s(val, ICC_CTLR_EL1);
+       write_sysreg_s(val, SYS_ICC_CTLR_EL1);
        isb();
 }
 
 static inline void gic_write_grpen1(u32 val)
 {
-       write_sysreg_s(val, ICC_GRPEN1_EL1);
+       write_sysreg_s(val, SYS_ICC_GRPEN1_EL1);
        isb();
 }
 
 static inline void gic_write_sgi1r(u64 val)
 {
-       write_sysreg_s(val, ICC_SGI1R_EL1);
+       write_sysreg_s(val, SYS_ICC_SGI1R_EL1);
 }
 
 static inline u32 gic_read_sre(void)
 {
-       return read_sysreg_s(ICC_SRE_EL1);
+       return read_sysreg_s(SYS_ICC_SRE_EL1);
 }
 
 static inline void gic_write_sre(u32 val)
 {
-       write_sysreg_s(val, ICC_SRE_EL1);
+       write_sysreg_s(val, SYS_ICC_SRE_EL1);
        isb();
 }
 
 static inline void gic_write_bpr1(u32 val)
 {
-       asm volatile("msr_s " __stringify(ICC_BPR1_EL1) ", %0" : : "r" (val));
+       write_sysreg_s(val, SYS_ICC_BPR1_EL1);
 }
 
 #define gic_read_typer(c)              readq_relaxed(c)