Merge tag 'tag-chrome-platform-for-v4.20' of git://git.kernel.org/pub/scm/linux/kerne...

[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / rockchip / rk3328.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 3f5a2944300fe2441f87ec1ac144d771f2cddbfe..e1a33dd981e0d2c1f93c0e333de0910fdbcb4fdd 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -151,6 +151,11 @@
                interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
        };
 
+       display_subsystem: display-subsystem {
+               compatible = "rockchip,display-subsystem";
+               ports = <&vop_out>;
+       };
+
        psci {
                compatible = "arm,psci-1.0", "arm,psci-0.2";
                method = "smc";
@@ -249,6 +254,12 @@
                        status = "disabled";
                };
 
+               grf_gpio: grf-gpio {
+                       compatible = "rockchip,rk3328-grf-gpio";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
                power: power-controller {
                        compatible = "rockchip,rk3328-power-controller";
                        #power-domain-cells = <1>;
@@ -274,7 +285,6 @@
                        mode-bootloader = <BOOT_FASTBOOT>;
                        mode-loader = <BOOT_BL_DOWNLOAD>;
                };
-
        };
 
        uart0: serial@ff110000 {
@@ -600,6 +610,28 @@
                status = "disabled";
        };
 
+       vop: vop@ff370000 {
+               compatible = "rockchip,rk3328-vop";
+               reg = <0x0 0xff370000 0x0 0x3efc>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
+               clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+               resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
+               reset-names = "axi", "ahb", "dclk";
+               iommus = <&vop_mmu>;
+               status = "disabled";
+
+               vop_out: port {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       vop_out_hdmi: endpoint@0 {
+                               reg = <0>;
+                               remote-endpoint = <&hdmi_in_vop>;
+                       };
+               };
+       };
+
        vop_mmu: iommu@ff373f00 {
                compatible = "rockchip,iommu";
                reg = <0x0 0xff373f00 0x0 0x100>;
@@ -611,6 +643,46 @@
                status = "disabled";
        };
 
+       hdmi: hdmi@ff3c0000 {
+               compatible = "rockchip,rk3328-dw-hdmi";
+               reg = <0x0 0xff3c0000 0x0 0x20000>;
+               reg-io-width = <4>;
+               interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru PCLK_HDMI>,
+                        <&cru SCLK_HDMI_SFC>;
+               clock-names = "iahb",
+                             "isfr";
+               phys = <&hdmiphy>;
+               phy-names = "hdmi";
+               pinctrl-names = "default";
+               pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
+               rockchip,grf = <&grf>;
+               status = "disabled";
+
+               ports {
+                       hdmi_in: port {
+                               hdmi_in_vop: endpoint {
+                                       remote-endpoint = <&vop_out_hdmi>;
+                               };
+                       };
+               };
+       };
+
+       hdmiphy: phy@ff430000 {
+               compatible = "rockchip,rk3328-hdmi-phy";
+               reg = <0x0 0xff430000 0x0 0x10000>;
+               interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
+               clock-names = "sysclk", "refoclk", "refpclk";
+               clock-output-names = "hdmi_phy";
+               #clock-cells = <0>;
+               nvmem-cells = <&efuse_cpu_version>;
+               nvmem-cell-names = "cpu-version";
+               #phy-cells = <0>;
+               status = "disabled";
+       };
+
        cru: clock-controller@ff440000 {
                compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
                reg = <0x0 0xff440000 0x0 0x1000>;