Merge branch 'x86-entry-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / renesas / r8a77965.dtsi
index 131f895ab778c9042c2f98366f5867b22de24841..4ae163220f6000b55e09844b75529a249dd4fd5d 100644 (file)
                        renesas,fcp = <&fcpvb0>;
                };
 
-               fcpvb0: fcp@fe96f000 {
-                       compatible = "renesas,fcpv";
-                       reg = <0 0xfe96f000 0 0x200>;
-                       clocks = <&cpg CPG_MOD 607>;
-                       power-domains = <&sysc R8A77965_PD_A3VP>;
-                       resets = <&cpg 607>;
-               };
-
                vspi0: vsp@fe9a0000 {
                        compatible = "renesas,vsp2";
                        reg = <0 0xfe9a0000 0 0x8000>;
                        renesas,fcp = <&fcpvi0>;
                };
 
-               fcpvi0: fcp@fe9af000 {
-                       compatible = "renesas,fcpv";
-                       reg = <0 0xfe9af000 0 0x200>;
-                       clocks = <&cpg CPG_MOD 611>;
-                       power-domains = <&sysc R8A77965_PD_A3VP>;
-                       resets = <&cpg 611>;
-               };
-
                vspd0: vsp@fea20000 {
                        compatible = "renesas,vsp2";
                        reg = <0 0xfea20000 0 0x5000>;
                        renesas,fcp = <&fcpvd0>;
                };
 
-               fcpvd0: fcp@fea27000 {
-                       compatible = "renesas,fcpv";
-                       reg = <0 0xfea27000 0 0x200>;
-                       clocks = <&cpg CPG_MOD 603>;
-                       power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
-                       resets = <&cpg 603>;
-               };
-
                vspd1: vsp@fea28000 {
                        compatible = "renesas,vsp2";
                        reg = <0 0xfea28000 0 0x5000>;
                        renesas,fcp = <&fcpvd1>;
                };
 
+               fcpvb0: fcp@fe96f000 {
+                       compatible = "renesas,fcpv";
+                       reg = <0 0xfe96f000 0 0x200>;
+                       clocks = <&cpg CPG_MOD 607>;
+                       power-domains = <&sysc R8A77965_PD_A3VP>;
+                       resets = <&cpg 607>;
+               };
+
+               fcpvd0: fcp@fea27000 {
+                       compatible = "renesas,fcpv";
+                       reg = <0 0xfea27000 0 0x200>;
+                       clocks = <&cpg CPG_MOD 603>;
+                       power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+                       resets = <&cpg 603>;
+               };
+
                fcpvd1: fcp@fea2f000 {
                        compatible = "renesas,fcpv";
                        reg = <0 0xfea2f000 0 0x200>;
                        resets = <&cpg 602>;
                };
 
+               fcpvi0: fcp@fe9af000 {
+                       compatible = "renesas,fcpv";
+                       reg = <0 0xfe9af000 0 0x200>;
+                       clocks = <&cpg CPG_MOD 611>;
+                       power-domains = <&sysc R8A77965_PD_A3VP>;
+                       resets = <&cpg 611>;
+               };
+
                csi20: csi2@fea80000 {
                        compatible = "renesas,r8a77965-csi2";
                        reg = <0 0xfea80000 0 0x10000>;
                        clock-names = "du.0", "du.1", "du.3";
                        status = "disabled";
 
-                       vsps = <&vspd0 0 &vspd1 0 &vspd0 1>;
+                       vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
 
                        ports {
                                #address-cells = <1>;