Merge tag 'microblaze-4.16-rc1' of git://git.monstr.eu/linux-2.6-microblaze

[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / mediatek / mt2712e.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 5d4e406bb35da6e154cc5f9166f2d0443e96e5a7..fdf66f4fe7c3166eb527a9f504f55e28ab5afce2 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -5,8 +5,10 @@
  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
  */
 
+#include <dt-bindings/clock/mt2712-clk.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/mt2712-power.h>
 
 / {
        compatible = "mediatek,mt2712";
@@ -14,6 +16,48 @@
        #address-cells = <2>;
        #size-cells = <2>;
 
+       cluster0_opp: opp_table0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+               opp00 {
+                       opp-hz = /bits/ 64 <598000000>;
+                       opp-microvolt = <1000000>;
+               };
+               opp01 {
+                       opp-hz = /bits/ 64 <702000000>;
+                       opp-microvolt = <1000000>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <793000000>;
+                       opp-microvolt = <1000000>;
+               };
+       };
+
+       cluster1_opp: opp_table1 {
+               compatible = "operating-points-v2";
+               opp-shared;
+               opp00 {
+                       opp-hz = /bits/ 64 <598000000>;
+                       opp-microvolt = <1000000>;
+               };
+               opp01 {
+                       opp-hz = /bits/ 64 <702000000>;
+                       opp-microvolt = <1000000>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <793000000>;
+                       opp-microvolt = <1000000>;
+               };
+               opp03 {
+                       opp-hz = /bits/ 64 <897000000>;
+                       opp-microvolt = <1000000>;
+               };
+               opp04 {
+                       opp-hz = /bits/ 64 <1001000000>;
+                       opp-microvolt = <1000000>;
+               };
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -39,6 +83,11 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a35";
                        reg = <0x000>;
+                       clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+                               <&topckgen CLK_TOP_F_MP0_PLL1>;
+                       clock-names = "cpu", "intermediate";
+                       proc-supply = <&cpus_fixed_vproc0>;
+                       operating-points-v2 = <&cluster0_opp>;
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
                };
 
@@ -47,6 +96,11 @@
                        compatible = "arm,cortex-a35";
                        reg = <0x001>;
                        enable-method = "psci";
+                       clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+                               <&topckgen CLK_TOP_F_MP0_PLL1>;
+                       clock-names = "cpu", "intermediate";
+                       proc-supply = <&cpus_fixed_vproc0>;
+                       operating-points-v2 = <&cluster0_opp>;
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
                };
 
@@ -55,6 +109,11 @@
                        compatible = "arm,cortex-a72";
                        reg = <0x200>;
                        enable-method = "psci";
+                       clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+                               <&topckgen CLK_TOP_F_BIG_PLL1>;
+                       clock-names = "cpu", "intermediate";
+                       proc-supply = <&cpus_fixed_vproc1>;
+                       operating-points-v2 = <&cluster1_opp>;
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
                };
 
@@ -98,6 +157,48 @@
                #clock-cells = <0>;
        };
 
+       clk26m: oscillator@0 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <26000000>;
+               clock-output-names = "clk26m";
+       };
+
+       clk32k: oscillator@1 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <32768>;
+               clock-output-names = "clk32k";
+       };
+
+       clkfpc: oscillator@2 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <50000000>;
+               clock-output-names = "clkfpc";
+       };
+
+       clkaud_ext_i_0: oscillator@3 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <6500000>;
+               clock-output-names = "clkaud_ext_i_0";
+       };
+
+       clkaud_ext_i_1: oscillator@4 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <196608000>;
+               clock-output-names = "clkaud_ext_i_1";
+       };
+
+       clkaud_ext_i_2: oscillator@5 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <180633600>;
+               clock-output-names = "clkaud_ext_i_2";
+       };
+
        timer {
                compatible = "arm,armv8-timer";
                interrupt-parent = <&gic>;
@@ -111,6 +212,39 @@
                              (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
        };
 
+       topckgen: syscon@10000000 {
+               compatible = "mediatek,mt2712-topckgen", "syscon";
+               reg = <0 0x10000000 0 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       infracfg: syscon@10001000 {
+               compatible = "mediatek,mt2712-infracfg", "syscon";
+               reg = <0 0x10001000 0 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       pericfg: syscon@10003000 {
+               compatible = "mediatek,mt2712-pericfg", "syscon";
+               reg = <0 0x10003000 0 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       scpsys: scpsys@10006000 {
+               compatible = "mediatek,mt2712-scpsys", "syscon";
+               #power-domain-cells = <1>;
+               reg = <0 0x10006000 0 0x1000>;
+               clocks = <&topckgen CLK_TOP_MM_SEL>,
+                        <&topckgen CLK_TOP_MFG_SEL>,
+                        <&topckgen CLK_TOP_VENC_SEL>,
+                        <&topckgen CLK_TOP_JPGDEC_SEL>,
+                        <&topckgen CLK_TOP_A1SYS_HP_SEL>,
+                        <&topckgen CLK_TOP_VDEC_SEL>;
+               clock-names = "mm", "mfg", "venc",
+                       "jpgdec", "audio", "vdec";
+               infracfg = <&infracfg>;
+       };
+
        uart5: serial@1000f000 {
                compatible = "mediatek,mt2712-uart",
                             "mediatek,mt6577-uart";
@@ -121,6 +255,18 @@
                status = "disabled";
        };
 
+       apmixedsys: syscon@10209000 {
+               compatible = "mediatek,mt2712-apmixedsys", "syscon";
+               reg = <0 0x10209000 0 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       mcucfg: syscon@10220000 {
+               compatible = "mediatek,mt2712-mcucfg", "syscon";
+               reg = <0 0x10220000 0 0x1000>;
+               #clock-cells = <1>;
+       };
+
        sysirq: interrupt-controller@10220a80 {
                compatible = "mediatek,mt2712-sysirq",
                             "mediatek,mt6577-sysirq";
@@ -192,5 +338,47 @@
                clock-names = "baud", "bus";
                status = "disabled";
        };
+
+       mfgcfg: syscon@13000000 {
+               compatible = "mediatek,mt2712-mfgcfg", "syscon";
+               reg = <0 0x13000000 0 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       mmsys: syscon@14000000 {
+               compatible = "mediatek,mt2712-mmsys", "syscon";
+               reg = <0 0x14000000 0 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       imgsys: syscon@15000000 {
+               compatible = "mediatek,mt2712-imgsys", "syscon";
+               reg = <0 0x15000000 0 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       bdpsys: syscon@15010000 {
+               compatible = "mediatek,mt2712-bdpsys", "syscon";
+               reg = <0 0x15010000 0 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       vdecsys: syscon@16000000 {
+               compatible = "mediatek,mt2712-vdecsys", "syscon";
+               reg = <0 0x16000000 0 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       vencsys: syscon@18000000 {
+               compatible = "mediatek,mt2712-vencsys", "syscon";
+               reg = <0 0x18000000 0 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       jpgdecsys: syscon@19000000 {
+               compatible = "mediatek,mt2712-jpgdecsys", "syscon";
+               reg = <0 0x19000000 0 0x1000>;
+               #clock-cells = <1>;
+       };
 };