Merge tag 'sound-fix-4.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai...

[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / marvell / armada-8040-mcbin.dts

diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
index 81de03ef860d8bb21e411f40292ba2aacebd500e..a66958ff4de6e493e6c2a6eaf62c546389d99397 100644 (file)
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
@@ -27,6 +27,7 @@
                ethernet0 = &cp0_eth0;
                ethernet1 = &cp1_eth0;
                ethernet2 = &cp1_eth1;
+               ethernet3 = &cp1_eth2;
        };
 
        /* Regulator labels correspond with schematics */
@@ -64,6 +65,42 @@
                compatible = "usb-nop-xceiv";
                vcc-supply = <&v_5v0_usb3_hst_vbus>;
        };
+
+       sfp_eth0: sfp-eth0 {
+               /* CON15,16 - CPM lane 4 */
+               compatible = "sff,sfp";
+               i2c-bus = <&sfpp0_i2c>;
+               los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
+               mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
+               tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
+               tx-fault-gpio  = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&cp1_sfpp0_pins>;
+       };
+
+       sfp_eth1: sfp-eth1 {
+               /* CON17,18 - CPS lane 4 */
+               compatible = "sff,sfp";
+               i2c-bus = <&sfpp1_i2c>;
+               los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
+               mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
+               tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
+               tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
+       };
+
+       sfp_eth3: sfp-eth3 {
+               /* CON3,4 - CPS lane 5 */
+               compatible = "sff,sfp";
+               i2c-bus = <&sfp_1g_i2c>;
+               los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
+               mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
+               tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
+               tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
+       };
 };
 
 &uart0 {
@@ -171,6 +208,10 @@
                marvell,pins = "mpp47";
                marvell,function = "gpio";
        };
+       cp0_sfp_1g_pins: sfp-1g-pins {
+               marvell,pins = "mpp51", "mpp53", "mpp54";
+               marvell,function = "gpio";
+       };
        cp0_pcie_pins: pcie-pins {
                marvell,pins = "mpp52";
                marvell,function = "gpio";
@@ -180,6 +221,10 @@
                               "mpp60", "mpp61";
                marvell,function = "sdio";
        };
+       cp0_sfpp1_pins: sfpp1-pins {
+               marvell,pins = "mpp62";
+               marvell,function = "gpio";
+       };
 };
 
 &cp0_xmdio {
@@ -188,11 +233,13 @@
        phy0: ethernet-phy@0 {
                compatible = "ethernet-phy-ieee802.3-c45";
                reg = <0>;
+               sfp = <&sfp_eth0>;
        };
 
        phy8: ethernet-phy@8 {
                compatible = "ethernet-phy-ieee802.3-c45";
                reg = <8>;
+               sfp = <&sfp_eth1>;
        };
 };
 
@@ -257,7 +304,22 @@
        phys = <&cp1_comphy0 1>;
 };
 
+&cp1_eth2 {
+       /* CPS Lane 5 */
+       status = "okay";
+       /* Network PHY */
+       phy-mode = "2500base-x";
+       managed = "in-band-status";
+       /* Generic PHY, providing serdes lanes */
+       phys = <&cp1_comphy5 2>;
+       sfp = <&sfp_eth3>;
+};
+
 &cp1_pinctrl {
+       cp1_sfpp1_pins: sfpp1-pins {
+               marvell,pins = "mpp8", "mpp10", "mpp11";
+               marvell,function = "gpio";
+       };
        cp1_spi1_pins: spi1-pins {
                marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
                marvell,function = "spi1";
@@ -266,6 +328,14 @@
                marvell,pins = "mpp6", "mpp7";
                marvell,function = "uart0";
        };
+       cp1_sfp_1g_pins: sfp-1g-pins {
+               marvell,pins = "mpp24";
+               marvell,function = "gpio";
+       };
+       cp1_sfpp0_pins: sfpp0-pins {
+               marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
+               marvell,function = "gpio";
+       };
 };
 
 /* J27 UART header */