Merge branch 'work.poll2' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs

[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / marvell / armada-70x0.dtsi

diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index 0e1a1e5be3998fc08a116911dbb560caaedc4f76..f63b4fbd642b1f58c0b5833f074958be64bc54c1 100644 (file)
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -44,25 +44,46 @@
  * Device Tree file for the Armada 70x0 SoC
  */
 
-#include "armada-cp110-master.dtsi"
-
 / {
        aliases {
-               gpio1 = &cpm_gpio1;
-               gpio2 = &cpm_gpio2;
+               gpio1 = &cp0_gpio1;
+               gpio2 = &cp0_gpio2;
+               spi1 = &cp0_spi0;
+               spi2 = &cp0_spi1;
        };
 };
 
-&cpm_gpio1 {
+/*
+ * Instantiate the CP110
+ */
+#define CP110_NAME             cp0
+#define CP110_BASE             f2000000
+#define CP110_PCIE_IO_BASE     0xf9000000
+#define CP110_PCIE_MEM_BASE    0xf6000000
+#define CP110_PCIE0_BASE       f2600000
+#define CP110_PCIE1_BASE       f2620000
+#define CP110_PCIE2_BASE       f2640000
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE_IO_BASE
+#undef CP110_PCIE_MEM_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
+
+&cp0_gpio1 {
        status = "okay";
 };
 
-&cpm_gpio2 {
+&cp0_gpio2 {
        status = "okay";
 };
 
-&cpm_syscon0 {
-       cpm_pinctrl: pinctrl {
+&cp0_syscon0 {
+       cp0_pinctrl: pinctrl {
                compatible = "marvell,armada-7k-pinctrl";
 
                nand_pins: nand-pins {