Merge tag 'acpi-5.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...

[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / freescale / imx8mq-evk.dts

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index f74b13aa5aa59ac962de33147ac5730d7df4a2cf..54737bf1772fef8e26af05f245c8eb9ecf5c3eb2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -37,7 +37,19 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_fec1>;
        phy-mode = "rgmii-id";
+       phy-handle = <&ethphy0>;
+       fsl,magic-packet;
        status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+               };
+       };
 };
 
 &i2c1 {
@@ -137,6 +149,29 @@
        status = "okay";
 };
 
+&usb3_phy1 {
+       status = "okay";
+};
+
+&usb_dwc3_1 {
+       dr_mode = "host";
+       status = "okay";
+};
+
+&qspi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_qspi>;
+       status = "okay";
+
+       n25q256a: flash@0 {
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "micron,n25q256a", "jedec,spi-nor";
+               spi-max-frequency = <29000000>;
+       };
+};
+
 &usdhc1 {
        pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc1>;
@@ -195,6 +230,18 @@
                >;
        };
 
+       pinctrl_qspi: qspigrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK       0x82
+                       MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B    0x82
+                       MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0   0x82
+                       MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1   0x82
+                       MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2   0x82
+                       MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3   0x82
+
+               >;
+       };
+
        pinctrl_reg_usdhc2: regusdhc2grpgpio {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19             0x41