Merge tag 'scsi-postmerge' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb...
[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / amlogic / meson-axg.dtsi
index b932a784b02afe61833991bc6f4fbaa8710e5a60..a80632641b39f8cb5dc8554aa2b2e85b6551e0ea 100644 (file)
@@ -7,6 +7,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/axg-clkc.h>
 
 / {
        compatible = "amlogic,meson-axg";
                #size-cells = <2>;
                ranges;
 
-               cbus: cbus@ffd00000 {
+               cbus: bus@ffd00000 {
                        compatible = "simple-bus";
                        reg = <0x0 0xffd00000 0x0 0x25000>;
                        #address-cells = <2>;
                        #size-cells = <2>;
                        ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
 
+                       pwm_ab: pwm@1b000 {
+                               compatible = "amlogic,meson-axg-ee-pwm";
+                               reg = <0x0 0x1b000 0x0 0x20>;
+                               #pwm-cells = <3>;
+                               status = "disabled";
+                       };
+
+                       pwm_cd: pwm@1a000 {
+                               compatible = "amlogic,meson-axg-ee-pwm";
+                               reg = <0x0 0x1a000 0x0 0x20>;
+                               #pwm-cells = <3>;
+                               status = "disabled";
+                       };
+
+                       reset: reset-controller@1004 {
+                               compatible = "amlogic,meson-axg-reset";
+                               reg = <0x0 0x01004 0x0 0x9c>;
+                               #reset-cells = <1>;
+                       };
+
+                       spicc0: spi@13000 {
+                               compatible = "amlogic,meson-axg-spicc";
+                               reg = <0x0 0x13000 0x0 0x3c>;
+                               interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clkc CLKID_SPICC0>;
+                               clock-names = "core";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       spicc1: spi@15000 {
+                               compatible = "amlogic,meson-axg-spicc";
+                               reg = <0x0 0x15000 0x0 0x3c>;
+                               interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clkc CLKID_SPICC1>;
+                               clock-names = "core";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
                        uart_A: serial@24000 {
                                compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
                                reg = <0x0 0x24000 0x0 0x14>;
                        };
                };
 
+               ethmac: ethernet@ff3f0000 {
+                       compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
+                       reg = <0x0 0xff3f0000 0x0 0x10000
+                               0x0 0xff634540 0x0 0x8>;
+                       interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "macirq";
+                       clocks = <&clkc CLKID_ETH>,
+                                <&clkc CLKID_FCLK_DIV2>,
+                                <&clkc CLKID_MPLL2>;
+                       clock-names = "stmmaceth", "clkin0", "clkin1";
+                       status = "disabled";
+               };
+
                gic: interrupt-controller@ffc01000 {
                        compatible = "arm,gic-400";
                        reg = <0x0 0xffc01000 0 0x1000>,
                        #address-cells = <0>;
                };
 
+               hiubus: bus@ff63c000 {
+                       compatible = "simple-bus";
+                       reg = <0x0 0xff63c000 0x0 0x1c00>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
+
+                       clkc: clock-controller@0 {
+                               compatible = "amlogic,axg-clkc";
+                               #clock-cells = <1>;
+                               reg = <0x0 0x0 0x0 0x320>;
+                       };
+               };
+
                mailbox: mailbox@ff63dc00 {
                        compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
                        reg = <0 0xff63dc00 0 0x400>;
                        #mbox-cells = <1>;
                };
 
+               periphs: periphs@ff634000 {
+                       compatible = "simple-bus";
+                       reg = <0x0 0xff634000 0x0 0x2000>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
+
+                       pinctrl_periphs: pinctrl@480 {
+                               compatible = "amlogic,meson-axg-periphs-pinctrl";
+                               #address-cells = <2>;
+                               #size-cells = <2>;
+                               ranges;
+
+                               gpio: bank@480 {
+                                       reg = <0x0 0x00480 0x0 0x40>,
+                                               <0x0 0x004e8 0x0 0x14>,
+                                               <0x0 0x00520 0x0 0x14>,
+                                               <0x0 0x00430 0x0 0x3c>;
+                                       reg-names = "mux", "pull", "pull-enable", "gpio";
+                                       gpio-controller;
+                                       #gpio-cells = <2>;
+                                       gpio-ranges = <&pinctrl_periphs 0 0 86>;
+                               };
+
+                               eth_rgmii_x_pins: eth-x-rgmii {
+                                       mux {
+                                               groups = "eth_mdio_x",
+                                                      "eth_mdc_x",
+                                                      "eth_rgmii_rx_clk_x",
+                                                      "eth_rx_dv_x",
+                                                      "eth_rxd0_x",
+                                                      "eth_rxd1_x",
+                                                      "eth_rxd2_rgmii",
+                                                      "eth_rxd3_rgmii",
+                                                      "eth_rgmii_tx_clk",
+                                                      "eth_txen_x",
+                                                      "eth_txd0_x",
+                                                      "eth_txd1_x",
+                                                      "eth_txd2_rgmii",
+                                                      "eth_txd3_rgmii";
+                                               function = "eth";
+                                       };
+                               };
+
+                               eth_rgmii_y_pins: eth-y-rgmii {
+                                       mux {
+                                               groups = "eth_mdio_y",
+                                                      "eth_mdc_y",
+                                                      "eth_rgmii_rx_clk_y",
+                                                      "eth_rx_dv_y",
+                                                      "eth_rxd0_y",
+                                                      "eth_rxd1_y",
+                                                      "eth_rxd2_rgmii",
+                                                      "eth_rxd3_rgmii",
+                                                      "eth_rgmii_tx_clk",
+                                                      "eth_txen_y",
+                                                      "eth_txd0_y",
+                                                      "eth_txd1_y",
+                                                      "eth_txd2_rgmii",
+                                                      "eth_txd3_rgmii";
+                                               function = "eth";
+                                       };
+                               };
+
+                               pwm_a_a_pins: pwm_a_a {
+                                       mux {
+                                               groups = "pwm_a_a";
+                                               function = "pwm_a";
+                                       };
+                               };
+
+                               pwm_a_x18_pins: pwm_a_x18 {
+                                       mux {
+                                               groups = "pwm_a_x18";
+                                               function = "pwm_a";
+                                       };
+                               };
+
+                               pwm_a_x20_pins: pwm_a_x20 {
+                                       mux {
+                                               groups = "pwm_a_x20";
+                                               function = "pwm_a";
+                                       };
+                               };
+
+                               pwm_a_z_pins: pwm_a_z {
+                                       mux {
+                                               groups = "pwm_a_z";
+                                               function = "pwm_a";
+                                       };
+                               };
+
+                               pwm_b_a_pins: pwm_b_a {
+                                       mux {
+                                               groups = "pwm_b_a";
+                                               function = "pwm_b";
+                                       };
+                               };
+
+                               pwm_b_x_pins: pwm_b_x {
+                                       mux {
+                                               groups = "pwm_b_x";
+                                               function = "pwm_b";
+                                       };
+                               };
+
+                               pwm_b_z_pins: pwm_b_z {
+                                       mux {
+                                               groups = "pwm_b_z";
+                                               function = "pwm_b";
+                                       };
+                               };
+
+                               pwm_c_a_pins: pwm_c_a {
+                                       mux {
+                                               groups = "pwm_c_a";
+                                               function = "pwm_c";
+                                       };
+                               };
+
+                               pwm_c_x10_pins: pwm_c_x10 {
+                                       mux {
+                                               groups = "pwm_c_x10";
+                                               function = "pwm_c";
+                                       };
+                               };
+
+                               pwm_c_x17_pins: pwm_c_x17 {
+                                       mux {
+                                               groups = "pwm_c_x17";
+                                               function = "pwm_c";
+                                       };
+                               };
+
+                               pwm_d_x11_pins: pwm_d_x11 {
+                                       mux {
+                                               groups = "pwm_d_x11";
+                                               function = "pwm_d";
+                                       };
+                               };
+
+                               pwm_d_x16_pins: pwm_d_x16 {
+                                       mux {
+                                               groups = "pwm_d_x16";
+                                               function = "pwm_d";
+                                       };
+                               };
+
+                               spi0_pins: spi0 {
+                                       mux {
+                                               groups = "spi0_miso",
+                                                       "spi0_mosi",
+                                                       "spi0_clk";
+                                               function = "spi0";
+                                       };
+                               };
+
+                               spi0_ss0_pins: spi0_ss0 {
+                                       mux {
+                                               groups = "spi0_ss0";
+                                               function = "spi0";
+                                       };
+                               };
+
+                               spi0_ss1_pins: spi0_ss1 {
+                                       mux {
+                                               groups = "spi0_ss1";
+                                               function = "spi0";
+                                       };
+                               };
+
+                               spi0_ss2_pins: spi0_ss2 {
+                                       mux {
+                                               groups = "spi0_ss2";
+                                               function = "spi0";
+                                       };
+                               };
+
+
+                               spi1_a_pins: spi1_a {
+                                       mux {
+                                               groups = "spi1_miso_a",
+                                                       "spi1_mosi_a",
+                                                       "spi1_clk_a";
+                                               function = "spi1";
+                                       };
+                               };
+
+                               spi1_ss0_a_pins: spi1_ss0_a {
+                                       mux {
+                                               groups = "spi1_ss0_a";
+                                               function = "spi1";
+                                       };
+                               };
+
+                               spi1_ss1_pins: spi1_ss1 {
+                                       mux {
+                                               groups = "spi1_ss1";
+                                               function = "spi1";
+                                       };
+                               };
+
+                               spi1_x_pins: spi1_x {
+                                       mux {
+                                               groups = "spi1_miso_x",
+                                                       "spi1_mosi_x",
+                                                       "spi1_clk_x";
+                                               function = "spi1";
+                                       };
+                               };
+
+                               spi1_ss0_x_pins: spi1_ss0_x {
+                                       mux {
+                                               groups = "spi1_ss0_x";
+                                               function = "spi1";
+                                       };
+                               };
+                       };
+               };
+
                sram: sram@fffc0000 {
                        compatible = "amlogic,meson-axg-sram", "mmio-sram";
                        reg = <0x0 0xfffc0000 0x0 0x20000>;
                        };
                };
 
-               aobus: aobus@ff800000 {
+               aobus: bus@ff800000 {
                        compatible = "simple-bus";
                        reg = <0x0 0xff800000 0x0 0x100000>;
                        #address-cells = <2>;
                        #size-cells = <2>;
                        ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
 
+                       pinctrl_aobus: pinctrl@14 {
+                               compatible = "amlogic,meson-axg-aobus-pinctrl";
+                               #address-cells = <2>;
+                               #size-cells = <2>;
+                               ranges;
+
+                               gpio_ao: bank@14 {
+                                       reg = <0x0 0x00014 0x0 0x8>,
+                                               <0x0 0x0002c 0x0 0x4>,
+                                               <0x0 0x00024 0x0 0x8>;
+                                       reg-names = "mux", "pull", "gpio";
+                                       gpio-controller;
+                                       #gpio-cells = <2>;
+                                       gpio-ranges = <&pinctrl_aobus 0 0 15>;
+                               };
+
+                               remote_input_ao_pins: remote_input_ao {
+                                       mux {
+                                               groups = "remote_input_ao";
+                                               function = "remote_input_ao";
+                                       };
+                               };
+                       };
+
+                       pwm_AO_ab: pwm@7000 {
+                               compatible = "amlogic,meson-axg-ao-pwm";
+                               reg = <0x0 0x07000 0x0 0x20>;
+                               #pwm-cells = <3>;
+                               status = "disabled";
+                       };
+
+                       pwm_AO_cd: pwm@2000 {
+                               compatible = "amlogic,axg-ao-pwm";
+                               reg = <0x0 0x02000  0x0 0x20>;
+                               #pwm-cells = <3>;
+                               status = "disabled";
+                       };
+
                        uart_AO: serial@3000 {
                                compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
                                reg = <0x0 0x3000 0x0 0x18>;
                                interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
-                               clocks = <&xtal>, <&xtal>, <&xtal>;
+                               clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
                                clock-names = "xtal", "pclk", "baud";
                                status = "disabled";
                        };
                                compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
                                reg = <0x0 0x4000 0x0 0x18>;
                                interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
-                               clocks = <&xtal>, <&xtal>, <&xtal>;
+                               clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
                                clock-names = "xtal", "pclk", "baud";
                                status = "disabled";
                        };
+
+                       ir: ir@8000 {
+                               compatible = "amlogic,meson-gxbb-ir";
+                               reg = <0x0 0x8000 0x0 0x20>;
+                               interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
+                               status = "disabled";
+                       };
                };
        };
 };