ARM: Fix wrong register in proc-arm6_7.S data abort handler

[sfrench/cifs-2.6.git] / arch / arm / mm / proc-arm6_7.S

diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 3f9cd3d8f6d508c447e46c5cf29ca078dd1b630b..795dc615f43bb6f4b6513f4ac6a17a287911876e 100644 (file)
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -41,7 +41,7 @@ ENTRY(cpu_arm7_dcache_clean_area)
 ENTRY(cpu_arm7_data_abort)
        mrc     p15, 0, r1, c5, c0, 0           @ get FSR
        mrc     p15, 0, r0, c6, c0, 0           @ get FAR
-       ldr     r8, [r0]                        @ read arm instruction
+       ldr     r8, [r2]                        @ read arm instruction
        tst     r8, #1 << 20                    @ L = 0 -> write?
        orreq   r1, r1, #1 << 11                @ yes.
        and     r7, r8, #15 << 24