ARM: entry: data abort: always use r6 for offset

[sfrench/cifs-2.6.git] / arch / arm / mm / proc-arm6_7.S

diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 5f79dc4ce3fbc98d76d32423b7b0dcb619ffe778..4d963114c66b3e0d4b087fe94a6417f44c43c15b 100644 (file)
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -29,8 +29,9 @@ ENTRY(cpu_arm7_dcache_clean_area)
 /*
  * Function: arm6_7_data_abort ()
  *
- * Params  : r2 = address of aborted instruction
- *        : sp = pointer to registers
+ * Params  : r2 = pt_regs
+ *        : r4 = aborted context pc
+ *        : r5 = aborted context psr
  *
  * Purpose : obtain information about current aborted instruction
  *
@@ -41,7 +42,7 @@ ENTRY(cpu_arm7_dcache_clean_area)
 ENTRY(cpu_arm7_data_abort)
        mrc     p15, 0, r1, c5, c0, 0           @ get FSR
        mrc     p15, 0, r0, c6, c0, 0           @ get FAR
-       ldr     r8, [r2]                        @ read arm instruction
+       ldr     r8, [r4]                        @ read arm instruction
        tst     r8, #1 << 20                    @ L = 0 -> write?
        orreq   r1, r1, #1 << 11                @ yes.
        and     r7, r8, #15 << 24
@@ -49,7 +50,7 @@ ENTRY(cpu_arm7_data_abort)
        nop
 
 /* 0 */        b       .data_unknown
-/* 1 */        mov     pc, lr                          @ swp
+/* 1 */        b       do_DataAbort                    @ swp
 /* 2 */        b       .data_unknown
 /* 3 */        b       .data_unknown
 /* 4 */        b       .data_arm_lateldrpostconst      @ ldr   rd, [rn], #m
@@ -60,79 +61,77 @@ ENTRY(cpu_arm7_data_abort)
 /* 9 */        b       .data_arm_ldmstm                @ ldm*b rn, <rlist>
 /* a */        b       .data_unknown
 /* b */        b       .data_unknown
-/* c */        mov     pc, lr                          @ ldc   rd, [rn], #m    @ Same as ldr   rd, [rn], #m
-/* d */        mov     pc, lr                          @ ldc   rd, [rn, #m]
+/* c */        b       do_DataAbort                    @ ldc   rd, [rn], #m    @ Same as ldr   rd, [rn], #m
+/* d */        b       do_DataAbort                    @ ldc   rd, [rn, #m]
 /* e */        b       .data_unknown
 /* f */
 .data_unknown: @ Part of jumptable
-       mov     r0, r2
+       mov     r0, r4
        mov     r1, r8
-       mov     r2, sp
-       bl      baddataabort
-       b       ret_from_exception
+       b       baddataabort
 
 ENTRY(cpu_arm6_data_abort)
        mrc     p15, 0, r1, c5, c0, 0           @ get FSR
        mrc     p15, 0, r0, c6, c0, 0           @ get FAR
-       ldr     r8, [r2]                        @ read arm instruction
+       ldr     r8, [r4]                        @ read arm instruction
        tst     r8, #1 << 20                    @ L = 0 -> write?
        orreq   r1, r1, #1 << 11                @ yes.
        and     r7, r8, #14 << 24
        teq     r7, #8 << 24                    @ was it ldm/stm
-       movne   pc, lr
+       bne     do_DataAbort
 
 .data_arm_ldmstm:
        tst     r8, #1 << 21                    @ check writeback bit
-       moveq   pc, lr                          @ no writeback -> no fixup
+       beq     do_DataAbort                    @ no writeback -> no fixup
        mov     r7, #0x11
        orr     r7, r7, #0x1100
        and     r6, r8, r7
-       and     r2, r8, r7, lsl #1
-       add     r6, r6, r2, lsr #1
-       and     r2, r8, r7, lsl #2
-       add     r6, r6, r2, lsr #2
-       and     r2, r8, r7, lsl #3
-       add     r6, r6, r2, lsr #3
+       and     r9, r8, r7, lsl #1
+       add     r6, r6, r9, lsr #1
+       and     r9, r8, r7, lsl #2
+       add     r6, r6, r9, lsr #2
+       and     r9, r8, r7, lsl #3
+       add     r6, r6, r9, lsr #3
        add     r6, r6, r6, lsr #8
        add     r6, r6, r6, lsr #4
        and     r6, r6, #15                     @ r6 = no. of registers to transfer.
        and     r5, r8, #15 << 16               @ Extract 'n' from instruction
-       ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
+       ldr     r7, [r2, r5, lsr #14]           @ Get register 'Rn'
        tst     r8, #1 << 23                    @ Check U bit
        subne   r7, r7, r6, lsl #2              @ Undo increment
        addeq   r7, r7, r6, lsl #2              @ Undo decrement
-       str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
-       mov     pc, lr
+       str     r7, [r2, r5, lsr #14]           @ Put register 'Rn'
+       b       do_DataAbort
 
 .data_arm_apply_r6_and_rn:
        and     r5, r8, #15 << 16               @ Extract 'n' from instruction
-       ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
+       ldr     r7, [r2, r5, lsr #14]           @ Get register 'Rn'
        tst     r8, #1 << 23                    @ Check U bit
        subne   r7, r7, r6                      @ Undo incrmenet
        addeq   r7, r7, r6                      @ Undo decrement
-       str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
-       mov     pc, lr
+       str     r7, [r2, r5, lsr #14]           @ Put register 'Rn'
+       b       do_DataAbort
 
 .data_arm_lateldrpreconst:
        tst     r8, #1 << 21                    @ check writeback bit
-       moveq   pc, lr                          @ no writeback -> no fixup
+       beq     do_DataAbort                    @ no writeback -> no fixup
 .data_arm_lateldrpostconst:
-       movs    r2, r8, lsl #20                 @ Get offset
-       moveq   pc, lr                          @ zero -> no fixup
+       movs    r6, r8, lsl #20                 @ Get offset
+       beq     do_DataAbort                    @ zero -> no fixup
        and     r5, r8, #15 << 16               @ Extract 'n' from instruction
-       ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
+       ldr     r7, [r2, r5, lsr #14]           @ Get register 'Rn'
        tst     r8, #1 << 23                    @ Check U bit
-       subne   r7, r7, r2, lsr #20             @ Undo increment
-       addeq   r7, r7, r2, lsr #20             @ Undo decrement
-       str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
-       mov     pc, lr
+       subne   r7, r7, r6, lsr #20             @ Undo increment
+       addeq   r7, r7, r6, lsr #20             @ Undo decrement
+       str     r7, [r2, r5, lsr #14]           @ Put register 'Rn'
+       b       do_DataAbort
 
 .data_arm_lateldrprereg:
        tst     r8, #1 << 21                    @ check writeback bit
-       moveq   pc, lr                          @ no writeback -> no fixup
+       beq     do_DataAbort                    @ no writeback -> no fixup
 .data_arm_lateldrpostreg:
        and     r7, r8, #15                     @ Extract 'm' from instruction
-       ldr     r6, [sp, r7, lsl #2]            @ Get register 'Rm'
+       ldr     r6, [r2, r7, lsl #2]            @ Get register 'Rm'
        mov     r5, r8, lsr #7                  @ get shift count
        ands    r5, r5, #31
        and     r7, r8, #0x70                   @ get shift type