Merge git://git.kernel.org/pub/scm/linux/kernel/git/sfrench/cifs-2.6

[sfrench/cifs-2.6.git] / arch / arm / mm / Kconfig

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index ed9d32c2469e540d38be36fd9fb97e26460c2626..c0bfb8212b7742abda15da17ffd47b09c3fe24e2 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -28,6 +28,7 @@ config CPU_ARM610
 # ARM7TDMI
 config CPU_ARM7TDMI
        bool "Support ARM7TDMI processor"
+       depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_LV4T
        select CPU_CACHE_V4
@@ -78,6 +79,7 @@ config CPU_ARM720T
 # ARM740T
 config CPU_ARM740T
        bool "Support ARM740T processor" if ARCH_INTEGRATOR
+       depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_LV4T
        select CPU_CACHE_V3     # although the core is v4t
@@ -93,8 +95,9 @@ config CPU_ARM740T
 # ARM9TDMI
 config CPU_ARM9TDMI
        bool "Support ARM9TDMI processor"
+       depends on !MMU
        select CPU_32v4T
-       select CPU_ABRT_EV4T
+       select CPU_ABRT_NOMMU
        select CPU_CACHE_V4
        help
          A 32-bit RISC microprocessor based on the ARM9 processor core
@@ -184,6 +187,39 @@ config CPU_ARM926T
          Say Y if you want support for the ARM926T processor.
          Otherwise, say N.
 
+# ARM940T
+config CPU_ARM940T
+       bool "Support ARM940T processor" if ARCH_INTEGRATOR
+       depends on !MMU
+       select CPU_32v4T
+       select CPU_ABRT_NOMMU
+       select CPU_CACHE_VIVT
+       select CPU_CP15_MPU
+       help
+         ARM940T is a member of the ARM9TDMI family of general-
+         purpose microprocessors with MPU and seperate 4KB
+         instruction and 4KB data cases, each with a 4-word line
+         length.
+
+         Say Y if you want support for the ARM940T processor.
+         Otherwise, say N.
+
+# ARM946E-S
+config CPU_ARM946E
+       bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
+       depends on !MMU
+       select CPU_32v5
+       select CPU_ABRT_NOMMU
+       select CPU_CACHE_VIVT
+       select CPU_CP15_MPU
+       help
+         ARM946E-S is a member of the ARM9E-S family of high-
+         performance, 32-bit system-on-chip processor solutions.
+         The TCM and ARMv5TE 32-bit instruction set is supported.
+
+         Say Y if you want support for the ARM946E-S processor.
+         Otherwise, say N.
+
 # ARM1020 - needs validating
 config CPU_ARM1020
        bool "Support ARM1020T (rev 0) processor"
@@ -356,6 +392,9 @@ config CPU_32v6
        bool
 
 # The abort model
+config CPU_ABRT_NOMMU
+       bool
+
 config CPU_ABRT_EV4
        bool
 
@@ -464,7 +503,7 @@ comment "Processor Features"
 
 config ARM_THUMB
        bool "Support Thumb user binaries"
-       depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
+       depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
        default y
        help
          Say Y if you want to include kernel support for running user space
@@ -485,6 +524,18 @@ config CPU_BIG_ENDIAN
          port must properly enable any big-endian related features
          of your chipset/board/processor.
 
+config CPU_HIGH_VECTOR
+       depends !MMU && CPU_CP15 && !CPU_ARM740T
+       bool "Select the High exception vector"
+       default n
+       help
+         Say Y here to select high exception vector(0xFFFF0000~).
+         The exception vector can be vary depending on the platform
+         design in nommu mode. If your platform needs to select
+         high exception vector, say Y.
+         Otherwise or if you are unsure, say N, and the low exception
+         vector (0x00000000~) will be used.
+
 config CPU_ICACHE_DISABLE
        bool "Disable I-Cache (I-bit)"
        depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
@@ -499,9 +550,22 @@ config CPU_DCACHE_DISABLE
          Say Y here to disable the processor data cache. Unless
          you have a reason not to or are unsure, say N.
 
+config CPU_DCACHE_SIZE
+       hex
+       depends on CPU_ARM740T || CPU_ARM946E
+       default 0x00001000 if CPU_ARM740T
+       default 0x00002000 # default size for ARM946E-S
+       help
+         Some cores are synthesizable to have various sized cache. For
+         ARM946E-S case, it can vary from 0KB to 1MB.
+         To support such cache operations, it is efficient to know the size
+         before compile time.
+         If your SoC is configured to have a different size, define the value
+         here with proper conditions.
+
 config CPU_DCACHE_WRITETHROUGH
        bool "Force write through D-cache"
-       depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
+       depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
        default y if CPU_ARM925T
        help
          Say Y here to use the data cache in writethrough mode. Unless you
@@ -509,7 +573,7 @@ config CPU_DCACHE_WRITETHROUGH
 
 config CPU_CACHE_ROUND_ROBIN
        bool "Round robin I and D cache replacement algorithm"
-       depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
+       depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
        help
          Say Y here to use the predictable round-robin cache replacement
          policy.  Unless you specifically require this or are unsure, say N.