Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jlbec...

[sfrench/cifs-2.6.git] / arch / arm / mm / Kconfig

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 346ae14824a5ea96365f6e9b66fa8f78cd8cd4bc..101105e5261070118f8039c5ecbcde350792f38f 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -735,6 +735,25 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
          Forget about fast user space cmpxchg support.
          It is just not possible.
 
+config DMA_CACHE_RWFO
+       bool "Enable read/write for ownership DMA cache maintenance"
+       depends on CPU_V6 && SMP
+       default y
+       help
+         The Snoop Control Unit on ARM11MPCore does not detect the
+         cache maintenance operations and the dma_{map,unmap}_area()
+         functions may leave stale cache entries on other CPUs. By
+         enabling this option, Read or Write For Ownership in the ARMv6
+         DMA cache maintenance functions is performed. These LDR/STR
+         instructions change the cache line state to shared or modified
+         so that the cache operation has the desired effect.
+
+         Note that the workaround is only valid on processors that do
+         not perform speculative loads into the D-cache. For such
+         processors, if cache maintenance operations are not broadcast
+         in hardware, other workarounds are needed (e.g. cache
+         maintenance broadcasting in software via FIQ).
+
 config OUTER_CACHE
        bool
 
@@ -794,6 +813,8 @@ config ARM_L1_CACHE_SHIFT
 
 config ARM_DMA_MEM_BUFFERABLE
        bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7
+       depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
+                    MACH_REALVIEW_PB11MP)
        default y if CPU_V6 || CPU_V7
        help
          Historically, the kernel has used strongly ordered mappings to