Merge branch 'ec' into release

[sfrench/cifs-2.6.git] / arch / arm / mach-s3c2410 / include / mach / regs-s3c2412-mem.h

diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
index a4bf2712317093570dce33efa6221d1aca4ecb04..fb635251509079c204af540d9c1ee7874cedc3d4 100644 (file)
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
@@ -14,9 +14,11 @@
 #ifndef __ASM_ARM_REGS_S3C2412_MEM
 #define __ASM_ARM_REGS_S3C2412_MEM
 
-#ifndef S3C2412_MEMREG
 #define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
-#endif
+#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
+
+#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
+#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
 
 #define S3C2412_BANKCFG                        S3C2412_MEMREG(0x00)
 #define S3C2412_BANKCON1               S3C2412_MEMREG(0x04)
@@ -26,4 +28,21 @@
 #define S3C2412_REFRESH                        S3C2412_MEMREG(0x10)
 #define S3C2412_TIMEOUT                        S3C2412_MEMREG(0x14)
 
+/* EBI control registers */
+
+#define S3C2412_EBI_PR                 S3C2412_EBIREG(0x00)
+#define S3C2412_EBI_BANKCFG            S3C2412_EBIREG(0x04)
+
+/* SSMC control registers */
+
+#define S3C2412_SSMC_BANK(x)           S3C2412_SSMC(x, 0x00)
+#define S3C2412_SMIDCYR(x)             S3C2412_SSMC(x, 0x00)
+#define S3C2412_SMBWSTRD(x)            S3C2412_SSMC(x, 0x04)
+#define S3C2412_SMBWSTWRR(x)           S3C2412_SSMC(x, 0x08)
+#define S3C2412_SMBWSTOENR(x)          S3C2412_SSMC(x, 0x0C)
+#define S3C2412_SMBWSTWENR(x)          S3C2412_SSMC(x, 0x10)
+#define S3C2412_SMBCR(x)               S3C2412_SSMC(x, 0x14)
+#define S3C2412_SMBSR(x)               S3C2412_SSMC(x, 0x18)
+#define S3C2412_SMBWSTBRDR(x)          S3C2412_SSMC(x, 0x1C)
+
 #endif /*  __ASM_ARM_REGS_S3C2412_MEM */