Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
[sfrench/cifs-2.6.git] / arch / arm / mach-omap2 / omap_hwmod_81xx_data.c
index b82b77cff24c2c7ae5bb5ee59fa16d88301c34c9..310afe474ec46a5d0674ab0d62d811c50c342ed6 100644 (file)
  */
 #define DM81XX_CM_DEFAULT_OFFSET       0x500
 #define DM81XX_CM_DEFAULT_USB_CLKCTRL  (0x558 - DM81XX_CM_DEFAULT_OFFSET)
+#define DM81XX_CM_DEFAULT_SATA_CLKCTRL (0x560 - DM81XX_CM_DEFAULT_OFFSET)
 
 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
@@ -973,6 +974,38 @@ static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
        .user           = OCP_USER_MPU,
 };
 
+static struct omap_hwmod_class_sysconfig dm81xx_sata_sysc = {
+       .sysc_offs      = 0x1100,
+       .sysc_flags     = SYSC_HAS_SIDLEMODE,
+       .idlemodes      = SIDLE_FORCE,
+       .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class dm81xx_sata_hwmod_class = {
+       .name   = "sata",
+       .sysc   = &dm81xx_sata_sysc,
+};
+
+static struct omap_hwmod dm81xx_sata_hwmod = {
+       .name           = "sata",
+       .clkdm_name     = "default_sata_clkdm",
+       .flags          = HWMOD_NO_IDLEST,
+       .prcm = {
+               .omap4 = {
+                       .clkctrl_offs = DM81XX_CM_DEFAULT_SATA_CLKCTRL,
+                       .modulemode   = MODULEMODE_SWCTRL,
+               },
+       },
+       .class          = &dm81xx_sata_hwmod_class,
+};
+
+static struct omap_hwmod_ocp_if dm81xx_l4_hs__sata = {
+       .master         = &dm81xx_l4_hs_hwmod,
+       .slave          = &dm81xx_sata_hwmod,
+       .clk            = "sysclk5_ck",
+       .user           = OCP_USER_MPU,
+};
+
 static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = {
        .rev_offs       = 0x0,
        .sysc_offs      = 0x110,
@@ -1474,6 +1507,7 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
        &dm81xx_l4_hs__emac0,
        &dm81xx_emac0__mdio,
        &dm816x_l4_hs__emac1,
+       &dm81xx_l4_hs__sata,
        &dm81xx_alwon_l3_fast__tpcc,
        &dm81xx_alwon_l3_fast__tptc0,
        &dm81xx_alwon_l3_fast__tptc1,