Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs...

[sfrench/cifs-2.6.git] / arch / arm / mach-mx5 / cpu.c

diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index d40671da4372a09a0e043a48bd1f6a8c7c44e60b..472bdfab2e552e3d7974c0a42a1477c444c84fe2 100644 (file)
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -21,6 +21,7 @@
 static int cpu_silicon_rev = -1;
 
 #define IIM_SREV 0x24
+#define MX50_HW_ADADIG_DIGPROG 0xB0
 
 static int get_mx51_srev(void)
 {
@@ -51,6 +52,26 @@ int mx51_revision(void)
 }
 EXPORT_SYMBOL(mx51_revision);
 
+void mx51_display_revision(void)
+{
+       int rev;
+       char *srev;
+       rev = mx51_revision();
+
+       switch (rev) {
+       case IMX_CHIP_REVISION_2_0:
+               srev = IMX_CHIP_REVISION_2_0_STRING;
+               break;
+       case IMX_CHIP_REVISION_3_0:
+               srev = IMX_CHIP_REVISION_3_0_STRING;
+               break;
+       default:
+               srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
+       }
+       printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev);
+}
+EXPORT_SYMBOL(mx51_display_revision);
+
 #ifdef CONFIG_NEON
 
 /*
@@ -78,11 +99,16 @@ static int get_mx53_srev(void)
        void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
        u32 rev = readl(iim_base + IIM_SREV) & 0xff;
 
-       if (rev == 0x0)
+       switch (rev) {
+       case 0x0:
                return IMX_CHIP_REVISION_1_0;
-       else if (rev == 0x10)
+       case 0x2:
                return IMX_CHIP_REVISION_2_0;
-       return 0;
+       case 0x3:
+               return IMX_CHIP_REVISION_2_1;
+       default:
+               return IMX_CHIP_REVISION_UNKNOWN;
+       }
 }
 
 /*
@@ -102,6 +128,44 @@ int mx53_revision(void)
 }
 EXPORT_SYMBOL(mx53_revision);
 
+static int get_mx50_srev(void)
+{
+       void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
+       u32 rev;
+
+       if (!anatop) {
+               cpu_silicon_rev = -EINVAL;
+               return 0;
+       }
+
+       rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
+       rev &= 0xff;
+
+       iounmap(anatop);
+       if (rev == 0x0)
+               return IMX_CHIP_REVISION_1_0;
+       else if (rev == 0x1)
+               return IMX_CHIP_REVISION_1_1;
+       return 0;
+}
+
+/*
+ * Returns:
+ *     the silicon revision of the cpu
+ *     -EINVAL - not a mx50
+ */
+int mx50_revision(void)
+{
+       if (!cpu_is_mx50())
+               return -EINVAL;
+
+       if (cpu_silicon_rev == -1)
+               cpu_silicon_rev = get_mx50_srev();
+
+       return cpu_silicon_rev;
+}
+EXPORT_SYMBOL(mx50_revision);
+
 static int __init post_cpu_init(void)
 {
        unsigned int reg;