Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

[sfrench/cifs-2.6.git] / arch / arm / mach-mx3 / clock.c

diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
index a68fcf981edf124678efa99695cf7efe6cd2cbc4..8b14239724c97fe90746878f6c3727f62bdf7066 100644 (file)
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock.c
@@ -483,7 +483,7 @@ DEFINE_CLOCK(i2c3_clk,    2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);
 DEFINE_CLOCK(mpeg4_clk,   0, MXC_CCM_CGR1,  0, NULL, NULL, &ahb_clk);
 DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1,  2, mstick1_get_rate, NULL, &usb_pll_clk);
 DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1,  4, mstick2_get_rate, NULL, &usb_pll_clk);
-DEFINE_CLOCK1(csi_clk,    0, MXC_CCM_CGR1,  6, csi, NULL, &ahb_clk);
+DEFINE_CLOCK1(csi_clk,    0, MXC_CCM_CGR1,  6, csi, NULL, &serial_pll_clk);
 DEFINE_CLOCK(rtc_clk,     0, MXC_CCM_CGR1,  8, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(wdog_clk,    0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(pwm_clk,     0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
@@ -566,13 +566,18 @@ int __init mx31_clocks_init(unsigned long fref)
        u32 reg;
        int i;
 
-       mxc_set_cpu_type(MXC_CPU_MX31);
-
        ckih_rate = fref;
 
        for (i = 0; i < ARRAY_SIZE(lookups); i++)
                clkdev_add(&lookups[i]);
 
+       /* change the csi_clk parent if necessary */
+       reg = __raw_readl(MXC_CCM_CCMR);
+       if (!(reg & MXC_CCM_CCMR_CSCS))
+               if (clk_set_parent(&csi_clk, &usb_pll_clk))
+                       pr_err("%s: error changing csi_clk parent\n", __func__);
+
+
        /* Turn off all possible clocks */
        __raw_writel((3 << 4), MXC_CCM_CGR0);
        __raw_writel(0, MXC_CCM_CGR1);
@@ -581,6 +586,12 @@ int __init mx31_clocks_init(unsigned long fref)
                                           MX32, but still required to be set */
                     MXC_CCM_CGR2);
 
+       /*
+        * Before turning off usb_pll make sure ipg_per_clk is generated
+        * by ipg_clk and not usb_pll.
+        */
+       __raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR);
+
        usb_pll_disable(&usb_pll_clk);
 
        pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));