Merge branches 'alignment', 'fixes', 'l2c' (early part) and 'misc' into for-next

[sfrench/cifs-2.6.git] / arch / arm / kernel / entry-armv.S

diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 1879e8dd2acc18a7837f0eee71beb8241c1aa9c0..52a949a8077d3329fc674cbbda7645673e484371 100644 (file)
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -344,7 +344,7 @@ ENDPROC(__pabt_svc)
        @
        @ Enable the alignment trap while in kernel mode
        @
-       alignment_trap r0
+       alignment_trap r0, .LCcralign
 
        @
        @ Clear FP to mark the first stack frame
@@ -413,6 +413,11 @@ __und_usr:
        @
        adr     r9, BSYM(ret_from_exception)
 
+       @ IRQs must be enabled before attempting to read the instruction from
+       @ user space since that could cause a page/translation fault if the
+       @ page table was modified by another CPU.
+       enable_irq
+
        tst     r3, #PSR_T_BIT                  @ Thumb mode?
        bne     __und_usr_thumb
        sub     r4, r2, #4                      @ ARM instr at LR - 4
@@ -484,7 +489,8 @@ ENDPROC(__und_usr)
  */
        .pushsection .fixup, "ax"
        .align  2
-4:     mov     pc, r9
+4:     str     r4, [sp, #S_PC]                 @ retry current instruction
+       mov     pc, r9
        .popsection
        .pushsection __ex_table,"a"
        .long   1b, 4b
@@ -517,7 +523,7 @@ ENDPROC(__und_usr)
  *  r9  = normal "successful" return address
  *  r10 = this threads thread_info structure
  *  lr  = unrecognised instruction return address
- * IRQs disabled, FIQs enabled.
+ * IRQs enabled, FIQs enabled.
  */
        @
        @ Fall-through from Thumb-2 __und_usr
@@ -624,7 +630,6 @@ call_fpe:
 #endif
 
 do_fpe:
-       enable_irq
        ldr     r4, .LCfp
        add     r10, r10, #TI_FPSTATE           @ r10 = workspace
        ldr     pc, [r4]                        @ Call FP module USR entry point
@@ -652,8 +657,7 @@ __und_usr_fault_32:
        b       1f
 __und_usr_fault_16:
        mov     r1, #2
-1:     enable_irq
-       mov     r0, sp
+1:     mov     r0, sp
        adr     lr, BSYM(ret_from_exception)
        b       __und_fault
 ENDPROC(__und_usr_fault_32)
@@ -1143,11 +1147,8 @@ __vectors_start:
        .data
 
        .globl  cr_alignment
-       .globl  cr_no_alignment
 cr_alignment:
        .space  4
-cr_no_alignment:
-       .space  4
 
 #ifdef CONFIG_MULTI_IRQ_HANDLER
        .globl  handle_arch_irq