Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / vf-colibri.dtsi

diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index 226a86ffd3c9c87da92cc6428237183bd393c635..b7417094dc11c32578856090b2bfc22f4df6ddb8 100644 (file)
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -222,6 +222,39 @@
                        >;
                };
 
+               pinctrl_dcu0_1: dcu0grp_1 {
+                       fsl,pins = <
+                               VF610_PAD_PTE0__DCU0_HSYNC      0x1902
+                               VF610_PAD_PTE1__DCU0_VSYNC      0x1902
+                               VF610_PAD_PTE2__DCU0_PCLK       0x1902
+                               VF610_PAD_PTE4__DCU0_DE         0x1902
+                               VF610_PAD_PTE5__DCU0_R0         0x1902
+                               VF610_PAD_PTE6__DCU0_R1         0x1902
+                               VF610_PAD_PTE7__DCU0_R2         0x1902
+                               VF610_PAD_PTE8__DCU0_R3         0x1902
+                               VF610_PAD_PTE9__DCU0_R4         0x1902
+                               VF610_PAD_PTE10__DCU0_R5        0x1902
+                               VF610_PAD_PTE11__DCU0_R6        0x1902
+                               VF610_PAD_PTE12__DCU0_R7        0x1902
+                               VF610_PAD_PTE13__DCU0_G0        0x1902
+                               VF610_PAD_PTE14__DCU0_G1        0x1902
+                               VF610_PAD_PTE15__DCU0_G2        0x1902
+                               VF610_PAD_PTE16__DCU0_G3        0x1902
+                               VF610_PAD_PTE17__DCU0_G4        0x1902
+                               VF610_PAD_PTE18__DCU0_G5        0x1902
+                               VF610_PAD_PTE19__DCU0_G6        0x1902
+                               VF610_PAD_PTE20__DCU0_G7        0x1902
+                               VF610_PAD_PTE21__DCU0_B0        0x1902
+                               VF610_PAD_PTE22__DCU0_B1        0x1902
+                               VF610_PAD_PTE23__DCU0_B2        0x1902
+                               VF610_PAD_PTE24__DCU0_B3        0x1902
+                               VF610_PAD_PTE25__DCU0_B4        0x1902
+                               VF610_PAD_PTE26__DCU0_B5        0x1902
+                               VF610_PAD_PTE27__DCU0_B6        0x1902
+                               VF610_PAD_PTE28__DCU0_B7        0x1902
+                       >;
+               };
+
                pinctrl_dspi1: dspi1grp {
                        fsl,pins = <
                                VF610_PAD_PTD5__DSPI1_CS0               0x33e2