Merge branches 'arm/rockchip', 'arm/exynos', 'arm/smmu', 'x86/vt-d', 'x86/amd', ...

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / vexpress-v2p-ca9.dts

diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 23662b5a5e9d84554f34eb0fc3edad1ef029f4e6..d949facba37641b3b36f337cd3eefce7932280d9 100644 (file)
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -33,28 +33,28 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               cpu@0 {
+               A9_0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
                        next-level-cache = <&L2>;
                };
 
-               cpu@1 {
+               A9_1: cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
                        next-level-cache = <&L2>;
                };
 
-               cpu@2 {
+               A9_2: cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <2>;
                        next-level-cache = <&L2>;
                };
 
-               cpu@3 {
+               A9_3: cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <3>;
@@ -170,6 +170,7 @@
                compatible = "arm,pl310-cache";
                reg = <0x1e00a000 0x1000>;
                interrupts = <0 43 4>;
+               cache-unified;
                cache-level = <2>;
                arm,data-latency = <1 1 1>;
                arm,tag-latency = <1 1 1>;
@@ -181,6 +182,8 @@
                             <0 61 4>,
                             <0 62 4>,
                             <0 63 4>;
+               interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
+
        };
 
        dcc {