Merge tag 'for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power...

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / sun9i-a80.dtsi

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index d9532fb1ef65071936c047a25274b2b299c30dce..6fb292e0b662e1f8d91678490cf1c1ca75025d24 100644 (file)
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -56,6 +56,10 @@
        #size-cells = <2>;
        interrupt-parent = <&gic>;
 
+       aliases {
+               ethernet0 = &gmac;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -183,6 +187,37 @@
                        clock-output-names = "osc32k";
                };
 
+               /*
+                * The following two are dummy clocks, placeholders
+                * used in the gmac_tx clock. The gmac driver will
+                * choose one parent depending on the PHY interface
+                * mode, using clk_set_rate auto-reparenting.
+                *
+                * The actual TX clock rate is not controlled by the
+                * gmac_tx clock.
+                */
+               mii_phy_tx_clk: mii_phy_tx_clk {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <25000000>;
+                       clock-output-names = "mii_phy_tx";
+               };
+
+               gmac_int_tx_clk: gmac_int_tx_clk {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <125000000>;
+                       clock-output-names = "gmac_int_tx";
+               };
+
+               gmac_tx_clk: clk@800030 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun7i-a20-gmac-clk";
+                       reg = <0x00800030 0x4>;
+                       clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+                       clock-output-names = "gmac_tx";
+               };
+
                cpus_clk: clk@8001410 {
                        compatible = "allwinner,sun9i-a80-cpus-clk";
                        reg = <0x08001410 0x4>;
@@ -283,6 +318,23 @@
                        };
                };
 
+               gmac: ethernet@830000 {
+                       compatible = "allwinner,sun7i-a20-gmac";
+                       reg = <0x00830000 0x1054>;
+                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "macirq";
+                       clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
+                       clock-names = "stmmaceth", "allwinner_gmac_tx";
+                       resets = <&ccu RST_BUS_GMAC>;
+                       reset-names = "stmmaceth";
+                       snps,pbl = <2>;
+                       snps,fixed-burst;
+                       snps,force_sf_dma_mode;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
                ehci0: usb@a00000 {
                        compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
                        reg = <0x00a00000 0x100>;
@@ -948,6 +1000,19 @@
                        #size-cells = <0>;
                        #gpio-cells = <3>;
 
+                       gmac_rgmii_pins: gmac-rgmii-pins {
+                               allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+                                                "PA4", "PA5", "PA7", "PA8",
+                                                "PA9", "PA10", "PA12", "PA13",
+                                                "PA15", "PA16", "PA17";
+                               allwinner,function = "gmac";
+                               /*
+                                * data lines in RGMII mode use DDR mode
+                                * and need a higher signal drive strength
+                                */
+                               drive-strength = <40>;
+                       };
+
                        i2c3_pins: i2c3-pins {
                                pins = "PG10", "PG11";
                                function = "i2c3";