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Merge tag 'modules-next-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / sun5i-a13.dtsi
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 3490ef9ec6034b8d4fb0a100bca11152f1a5133d..f01c315bdc4b0e1a37b34e4456ef95fb92f01352 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -16,6 +16,11 @@
 / {
        interrupt-parent = <&intc>;
 
+       aliases {
+               serial0 = &uart1;
+               serial1 = &uart3;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -47,44 +52,48 @@
                        clock-frequency = <0>;
                };
 
-               osc24M: osc24M@01c20050 {
+               osc24M: clk@01c20050 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-osc-clk";
+                       compatible = "allwinner,sun4i-a10-osc-clk";
                        reg = <0x01c20050 0x4>;
                        clock-frequency = <24000000>;
+                       clock-output-names = "osc24M";
                };
 
-               osc32k: osc32k {
+               osc32k: clk@0 {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        clock-frequency = <32768>;
+                       clock-output-names = "osc32k";
                };
 
-               pll1: pll1@01c20000 {
+               pll1: clk@01c20000 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-pll1-clk";
+                       compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20000 0x4>;
                        clocks = <&osc24M>;
+                       clock-output-names = "pll1";
                };
 
-               pll4: pll4@01c20018 {
+               pll4: clk@01c20018 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-pll1-clk";
+                       compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20018 0x4>;
                        clocks = <&osc24M>;
+                       clock-output-names = "pll4";
                };
 
-               pll5: pll5@01c20020 {
+               pll5: clk@01c20020 {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-pll5-clk";
+                       compatible = "allwinner,sun4i-a10-pll5-clk";
                        reg = <0x01c20020 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll5_ddr", "pll5_other";
                };
 
-               pll6: pll6@01c20028 {
+               pll6: clk@01c20028 {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-pll6-clk";
+                       compatible = "allwinner,sun4i-a10-pll6-clk";
                        reg = <0x01c20028 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -93,21 +102,23 @@
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-cpu-clk";
+                       compatible = "allwinner,sun4i-a10-cpu-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+                       clock-output-names = "cpu";
                };
 
                axi: axi@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-axi-clk";
+                       compatible = "allwinner,sun4i-a10-axi-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&cpu>;
+                       clock-output-names = "axi";
                };
 
-               axi_gates: axi_gates@01c2005c {
+               axi_gates: clk@01c2005c {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-axi-gates-clk";
+                       compatible = "allwinner,sun4i-a10-axi-gates-clk";
                        reg = <0x01c2005c 0x4>;
                        clocks = <&axi>;
                        clock-output-names = "axi_dram";
@@ -115,12 +126,13 @@
 
                ahb: ahb@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-ahb-clk";
+                       compatible = "allwinner,sun4i-a10-ahb-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&axi>;
+                       clock-output-names = "ahb";
                };
 
-               ahb_gates: ahb_gates@01c20060 {
+               ahb_gates: clk@01c20060 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun5i-a13-ahb-gates-clk";
                        reg = <0x01c20060 0x8>;
@@ -135,12 +147,13 @@
 
                apb0: apb0@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb0-clk";
+                       compatible = "allwinner,sun4i-a10-apb0-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&ahb>;
+                       clock-output-names = "apb0";
                };
 
-               apb0_gates: apb0_gates@01c20068 {
+               apb0_gates: clk@01c20068 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun5i-a13-apb0-gates-clk";
                        reg = <0x01c20068 0x4>;
@@ -150,19 +163,21 @@
 
                apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-mux-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+                       clock-output-names = "apb1_mux";
                };
 
                apb1: apb1@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&apb1_mux>;
+                       clock-output-names = "apb1";
                };
 
-               apb1_gates: apb1_gates@01c2006c {
+               apb1_gates: clk@01c2006c {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun5i-a13-apb1-gates-clk";
                        reg = <0x01c2006c 0x4>;
@@ -173,7 +188,7 @@
 
                nand_clk: clk@01c20080 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20080 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "nand";
@@ -181,7 +196,7 @@
 
                ms_clk: clk@01c20084 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20084 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ms";
@@ -189,7 +204,7 @@
 
                mmc0_clk: clk@01c20088 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20088 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc0";
@@ -197,7 +212,7 @@
 
                mmc1_clk: clk@01c2008c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2008c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc1";
@@ -205,7 +220,7 @@
 
                mmc2_clk: clk@01c20090 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20090 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc2";
@@ -213,7 +228,7 @@
 
                ts_clk: clk@01c20098 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20098 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ts";
@@ -221,7 +236,7 @@
 
                ss_clk: clk@01c2009c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2009c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ss";
@@ -229,7 +244,7 @@
 
                spi0_clk: clk@01c200a0 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi0";
@@ -237,7 +252,7 @@
 
                spi1_clk: clk@01c200a4 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi1";
@@ -245,7 +260,7 @@
 
                spi2_clk: clk@01c200a8 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a8 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi2";
@@ -253,15 +268,24 @@
 
                ir0_clk: clk@01c200b0 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200b0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ir0";
                };
 
+               usb_clk: clk@01c200cc {
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       compatible = "allwinner,sun5i-a13-usb-clk";
+                       reg = <0x01c200cc 0x4>;
+                       clocks = <&pll6 1>;
+                       clock-output-names = "usb_ohci0", "usb_phy";
+               };
+
                mbus_clk: clk@01c2015c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2015c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mbus";
@@ -274,6 +298,71 @@
                #size-cells = <1>;
                ranges;
 
+               spi0: spi@01c05000 {
+                       compatible = "allwinner,sun4i-a10-spi";
+                       reg = <0x01c05000 0x1000>;
+                       interrupts = <10>;
+                       clocks = <&ahb_gates 20>, <&spi0_clk>;
+                       clock-names = "ahb", "mod";
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               spi1: spi@01c06000 {
+                       compatible = "allwinner,sun4i-a10-spi";
+                       reg = <0x01c06000 0x1000>;
+                       interrupts = <11>;
+                       clocks = <&ahb_gates 21>, <&spi1_clk>;
+                       clock-names = "ahb", "mod";
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               usbphy: phy@01c13400 {
+                       #phy-cells = <1>;
+                       compatible = "allwinner,sun5i-a13-usb-phy";
+                       reg = <0x01c13400 0x10 0x01c14800 0x4>;
+                       reg-names = "phy_ctrl", "pmu1";
+                       clocks = <&usb_clk 8>;
+                       clock-names = "usb_phy";
+                       resets = <&usb_clk 1>;
+                       reset-names = "usb1_reset";
+                       status = "disabled";
+               };
+
+               ehci0: usb@01c14000 {
+                       compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
+                       reg = <0x01c14000 0x100>;
+                       interrupts = <39>;
+                       clocks = <&ahb_gates 1>;
+                       phys = <&usbphy 1>;
+                       phy-names = "usb";
+                       status = "disabled";
+               };
+
+               ohci0: usb@01c14400 {
+                       compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
+                       reg = <0x01c14400 0x100>;
+                       interrupts = <40>;
+                       clocks = <&usb_clk 6>, <&ahb_gates 2>;
+                       phys = <&usbphy 1>;
+                       phy-names = "usb";
+                       status = "disabled";
+               };
+
+               spi2: spi@01c17000 {
+                       compatible = "allwinner,sun4i-a10-spi";
+                       reg = <0x01c17000 0x1000>;
+                       interrupts = <12>;
+                       clocks = <&ahb_gates 22>, <&spi2_clk>;
+                       clock-names = "ahb", "mod";
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
                intc: interrupt-controller@01c20400 {
                        compatible = "allwinner,sun4i-a10-ic";
                        reg = <0x01c20400 0x400>;
@@ -336,7 +425,7 @@
                };
 
                wdt: watchdog@01c20c90 {
-                       compatible = "allwinner,sun4i-wdt";
+                       compatible = "allwinner,sun4i-a10-wdt";
                        reg = <0x01c20c90 0x10>;
                };
 
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