Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / stm32h743.dtsi

diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 26de3157870110d22aa6c2508df4ba6ad7fbd871..bbfcbaca0b36bc30e44b63dd5bc9c7b9ef872f91 100644 (file)
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -42,6 +42,8 @@
 
 #include "skeleton.dtsi"
 #include "armv7-m.dtsi"
+#include <dt-bindings/clock/stm32h7-clks.h>
+#include <dt-bindings/mfd/stm32h7-rcc.h>
 
 / {
        clocks {
@@ -51,10 +53,16 @@
                        clock-frequency = <0>;
                };
 
-               timer_clk: timer-clk {
+               clk_lse: clk-lse {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
-                       clock-frequency = <125000000>;
+                       clock-frequency = <32768>;
+               };
+
+               clk_i2s: i2s_ckin {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <0>;
                };
        };
 
@@ -63,7 +71,33 @@
                        compatible = "st,stm32-timer";
                        reg = <0x40000c00 0x400>;
                        interrupts = <50>;
-                       clocks = <&timer_clk>;
+                       clocks = <&rcc TIM5_CK>;
+               };
+
+               lptimer1: timer@40002400 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "st,stm32-lptimer";
+                       reg = <0x40002400 0x400>;
+                       clocks = <&rcc LPTIM1_CK>;
+                       clock-names = "mux";
+                       status = "disabled";
+
+                       pwm {
+                               compatible = "st,stm32-pwm-lp";
+                               status = "disabled";
+                       };
+
+                       trigger@0 {
+                               compatible = "st,stm32-lptimer-trigger";
+                               reg = <0>;
+                               status = "disabled";
+                       };
+
+                       counter {
+                               compatible = "st,stm32-lptimer-counter";
+                               status = "disabled";
+                       };
                };
 
                usart2: serial@40004400 {
@@ -71,13 +105,13 @@
                        reg = <0x40004400 0x400>;
                        interrupts = <38>;
                        status = "disabled";
-                       clocks = <&timer_clk>;
+                       clocks = <&rcc USART2_CK>;
                };
 
                dac: dac@40007400 {
                        compatible = "st,stm32h7-dac-core";
                        reg = <0x40007400 0x400>;
-                       clocks = <&timer_clk>;
+                       clocks = <&rcc DAC12_CK>;
                        clock-names = "pclk";
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -103,8 +137,7 @@
                        reg = <0x40011000 0x400>;
                        interrupts = <37>;
                        status = "disabled";
-                       clocks = <&timer_clk>;
-
+                       clocks = <&rcc USART1_CK>;
                };
 
                dma1: dma@40020000 {
@@ -118,9 +151,10 @@
                                     <16>,
                                     <17>,
                                     <47>;
-                       clocks = <&timer_clk>;
+                       clocks = <&rcc DMA1_CK>;
                        #dma-cells = <4>;
                        st,mem2mem;
+                       dma-requests = <8>;
                        status = "disabled";
                };
 
@@ -135,17 +169,28 @@
                                     <68>,
                                     <69>,
                                     <70>;
-                       clocks = <&timer_clk>;
+                       clocks = <&rcc DMA2_CK>;
                        #dma-cells = <4>;
                        st,mem2mem;
+                       dma-requests = <8>;
                        status = "disabled";
                };
 
+               dmamux1: dma-router@40020800 {
+                       compatible = "st,stm32h7-dmamux";
+                       reg = <0x40020800 0x1c>;
+                       #dma-cells = <3>;
+                       dma-channels = <16>;
+                       dma-requests = <128>;
+                       dma-masters = <&dma1 &dma2>;
+                       clocks = <&rcc DMA1_CK>;
+               };
+
                adc_12: adc@40022000 {
                        compatible = "st,stm32h7-adc-core";
                        reg = <0x40022000 0x400>;
                        interrupts = <18>;
-                       clocks = <&timer_clk>;
+                       clocks = <&rcc ADC12_CK>;
                        clock-names = "bus";
                        interrupt-controller;
                        #interrupt-cells = <1>;
@@ -172,11 +217,121 @@
                        };
                };
 
+               mdma1: dma@52000000 {
+                       compatible = "st,stm32h7-mdma";
+                       reg = <0x52000000 0x1000>;
+                       interrupts = <122>;
+                       clocks = <&rcc MDMA_CK>;
+                       #dma-cells = <5>;
+                       dma-channels = <16>;
+                       dma-requests = <32>;
+               };
+
+               lptimer2: timer@58002400 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "st,stm32-lptimer";
+                       reg = <0x58002400 0x400>;
+                       clocks = <&rcc LPTIM2_CK>;
+                       clock-names = "mux";
+                       status = "disabled";
+
+                       pwm {
+                               compatible = "st,stm32-pwm-lp";
+                               status = "disabled";
+                       };
+
+                       trigger@1 {
+                               compatible = "st,stm32-lptimer-trigger";
+                               reg = <1>;
+                               status = "disabled";
+                       };
+
+                       counter {
+                               compatible = "st,stm32-lptimer-counter";
+                               status = "disabled";
+                       };
+               };
+
+               lptimer3: timer@58002800 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "st,stm32-lptimer";
+                       reg = <0x58002800 0x400>;
+                       clocks = <&rcc LPTIM3_CK>;
+                       clock-names = "mux";
+                       status = "disabled";
+
+                       pwm {
+                               compatible = "st,stm32-pwm-lp";
+                               status = "disabled";
+                       };
+
+                       trigger@2 {
+                               compatible = "st,stm32-lptimer-trigger";
+                               reg = <2>;
+                               status = "disabled";
+                       };
+               };
+
+               lptimer4: timer@58002c00 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "st,stm32-lptimer";
+                       reg = <0x58002c00 0x400>;
+                       clocks = <&rcc LPTIM4_CK>;
+                       clock-names = "mux";
+                       status = "disabled";
+
+                       pwm {
+                               compatible = "st,stm32-pwm-lp";
+                               status = "disabled";
+                       };
+               };
+
+               lptimer5: timer@58003000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "st,stm32-lptimer";
+                       reg = <0x58003000 0x400>;
+                       clocks = <&rcc LPTIM5_CK>;
+                       clock-names = "mux";
+                       status = "disabled";
+
+                       pwm {
+                               compatible = "st,stm32-pwm-lp";
+                               status = "disabled";
+                       };
+               };
+
+               vrefbuf: regulator@58003C00 {
+                       compatible = "st,stm32-vrefbuf";
+                       reg = <0x58003C00 0x8>;
+                       clocks = <&rcc VREF_CK>;
+                       regulator-min-microvolt = <1500000>;
+                       regulator-max-microvolt = <2500000>;
+                       status = "disabled";
+               };
+
+               rcc: reset-clock-controller@58024400 {
+                       compatible = "st,stm32h743-rcc", "st,stm32-rcc";
+                       reg = <0x58024400 0x400>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
+                       st,syscfg = <&pwrcfg>;
+               };
+
+               pwrcfg: power-config@58024800 {
+                       compatible = "syscon";
+                       reg = <0x58024800 0x400>;
+               };
+
                adc_3: adc@58026000 {
                        compatible = "st,stm32h7-adc-core";
                        reg = <0x58026000 0x400>;
                        interrupts = <127>;
-                       clocks = <&timer_clk>;
+                       clocks = <&rcc ADC3_CK>;
                        clock-names = "bus";
                        interrupt-controller;
                        #interrupt-cells = <1>;