Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / rk3288-veyron.dtsi

diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index 1d8bfed7830cabd9a58dfdbe16c92d96713edb45..8fc8eac699bf513f324e3762d05657911b6c0b1a 100644 (file)
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -23,11 +23,36 @@
                reg = <0x0 0x0 0x0 0x80000000>;
        };
 
-       gpio_keys: gpio-keys {
+       bt_activity: bt-activity {
                compatible = "gpio-keys";
+               pinctrl-names = "default";
+               pinctrl-0 = <&bt_host_wake>;
+
+               /*
+                * HACK: until we have an LPM driver, we'll use an
+                * ugly GPIO key to allow Bluetooth to wake from S3.
+                * This is expected to only be used by BT modules that
+                * use UART for comms.  For BT modules that talk over
+                * SDIO we should use a wakeup mechanism related to SDIO.
+                *
+                * Use KEY_RESERVED here since that will work as a wakeup but
+                * doesn't get reported to higher levels (so doesn't confuse
+                * Chrome).
+                */
+               bt-wake {
+                       label = "BT Wakeup";
+                       gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
+                       linux,code = <KEY_RESERVED>;
+                       wakeup-source;
+               };
+
+       };
 
+       power_button: power-button {
+               compatible = "gpio-keys";
                pinctrl-names = "default";
                pinctrl-0 = <&pwr_key_l>;
+
                power {
                        label = "Power";
                        gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
@@ -123,6 +148,10 @@
        cpu0-supply = <&vdd_cpu>;
 };
 
+&cpu_crit {
+       temperature = <100000>;
+};
+
 /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
 &cpu_opp_table {
        /delete-node/ opp-312000000;
@@ -162,8 +191,18 @@
        status = "okay";
 };
 
+&gpu_alert0 {
+       temperature = <72500>;
+};
+
+&gpu_crit {
+       temperature = <100000>;
+};
+
 &hdmi {
-       ddc-i2c-bus = <&i2c5>;
+       pinctrl-names = "default", "unwedge";
+       pinctrl-0 = <&hdmi_ddc>;
+       pinctrl-1 = <&hdmi_ddc_unwedge>;
        status = "okay";
 };
 
@@ -334,14 +373,6 @@
        i2c-scl-rising-time-ns = <300>;         /* 225ns measured */
 };
 
-&i2c5 {
-       status = "okay";
-
-       clock-frequency = <100000>;
-       i2c-scl-falling-time-ns = <300>;
-       i2c-scl-rising-time-ns = <1000>;
-};
-
 &io_domains {
        status = "okay";
 
@@ -394,6 +425,7 @@
 
        rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
        rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
+       rockchip,hw-tshut-temp = <125000>;
 };
 
 &uart0 {
@@ -455,12 +487,18 @@
                &ddr0_retention
                &ddrio_pwroff
                &global_pwroff
+
+               /* Wake only */
+               &bt_dev_wake_awake
        >;
        pinctrl-1 = <
                /* Common for sleep and wake, but no owners */
                &ddr0_retention
                &ddrio_pwroff
                &global_pwroff
+
+               /* Sleep only */
+               &bt_dev_wake_sleep
        >;
 
        pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
@@ -544,6 +582,10 @@
                        rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
+               bt_host_wake: bt-host-wake {
+                       rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>;
+               };
+
                /*
                 * We run sdio0 at max speed; bump up drive strength.
                 * We also have external pulls, so disable the internal ones.
@@ -562,6 +604,20 @@
                sdio0_clk: sdio0-clk {
                        rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;
                };
+
+               /*
+                * These pins are only present on very new veyron boards; on
+                * older boards bt_dev_wake is simply always high.  Note that
+                * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt
+                * to map this pin everywhere
+                */
+               bt_dev_wake_sleep: bt-dev-wake-sleep {
+                       rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>;
+               };
+
+               bt_dev_wake_awake: bt-dev-wake-awake {
+                       rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
+               };
        };
 
        tpm {