Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / r8a7779.dtsi

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 0c82097daffcdd8bd3ac5c0840c7cae0a039d277..b9bbcce69dfbd5b9efda7ae20a83752cf459c925 100644 (file)
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -14,6 +14,7 @@
 #include <dt-bindings/clock/r8a7779-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7779-sysc.h>
 
 / {
        compatible = "renesas,r8a7779";
@@ -34,18 +35,21 @@
                        compatible = "arm,cortex-a9";
                        reg = <1>;
                        clock-frequency = <1000000000>;
+                       power-domains = <&sysc R8A7779_PD_ARM1>;
                };
                cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <2>;
                        clock-frequency = <1000000000>;
+                       power-domains = <&sysc R8A7779_PD_ARM2>;
                };
                cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <3>;
                        clock-frequency = <1000000000>;
+                       power-domains = <&sysc R8A7779_PD_ARM3>;
                };
        };
 
@@ -173,7 +177,7 @@
                reg = <0xffc70000 0x1000>;
                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -184,7 +188,7 @@
                reg = <0xffc71000 0x1000>;
                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -195,7 +199,7 @@
                reg = <0xffc72000 0x1000>;
                interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -206,7 +210,7 @@
                reg = <0xffc73000 0x1000>;
                interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -218,7 +222,7 @@
                clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
                         <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
                clock-names = "fck", "brg_int", "scif_clk";
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -230,7 +234,7 @@
                clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
                         <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
                clock-names = "fck", "brg_int", "scif_clk";
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -242,7 +246,7 @@
                clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
                         <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
                clock-names = "fck", "brg_int", "scif_clk";
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -254,7 +258,7 @@
                clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
                         <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
                clock-names = "fck", "brg_int", "scif_clk";
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -266,7 +270,7 @@
                clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
                         <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
                clock-names = "fck", "brg_int", "scif_clk";
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -278,7 +282,7 @@
                clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
                         <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
                clock-names = "fck", "brg_int", "scif_clk";
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -300,7 +304,7 @@
                             <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
                clock-names = "fck";
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 
                #renesas,channels = <3>;
 
@@ -315,7 +319,7 @@
                             <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
                clock-names = "fck";
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 
                #renesas,channels = <3>;
 
@@ -330,7 +334,7 @@
                             <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
                clock-names = "fck";
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 
                #renesas,channels = <3>;
 
@@ -342,7 +346,7 @@
                reg = <0xfc600000 0x2000>;
                interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp1_clks R8A7779_CLK_SATA>;
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
        };
 
        sdhi0: sd@ffe4c000 {
@@ -350,7 +354,7 @@
                reg = <0xffe4c000 0x100>;
                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -359,7 +363,7 @@
                reg = <0xffe4d000 0x100>;
                interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -368,7 +372,7 @@
                reg = <0xffe4e000 0x100>;
                interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -377,7 +381,7 @@
                reg = <0xffe4f000 0x100>;
                interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -388,7 +392,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -399,7 +403,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -410,7 +414,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
        };
 
@@ -419,7 +423,7 @@
                reg = <0 0xfff80000 0 0x40000>;
                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp1_clks R8A7779_CLK_DU>;
-               power-domains = <&cpg_clocks>;
+               power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
                status = "disabled";
 
                ports {
@@ -585,4 +589,10 @@
                                "mmc1", "mmc0";
                };
        };
+
+       sysc: system-controller@ffd85000 {
+               compatible = "renesas,r8a7779-sysc";
+               reg = <0xffd85000 0x0200>;
+               #power-domain-cells = <1>;
+       };
 };