Merge tag 'bcm2835-dt-next-2017-03-30' into devicetree/fixes

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / r7s72100.dtsi

diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 1cf2bd0380901d1d6f8ec05cfc38e693defaddfe..0423996e4dccf612a0521546699d17df3ae9c360 100644 (file)
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -51,6 +51,20 @@
                        clock-frequency = <0>;
                };
 
+               rtc_x1_clk: rtc_x1 {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       /* If clk present, value must be set by board to 32678 */
+                       clock-frequency = <0>;
+               };
+
+               rtc_x3_clk: rtc_x3 {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       /* If clk present, value must be set by board to 4000000 */
+                       clock-frequency = <0>;
+               };
+
                /* Fixed factor clocks */
                b_clk: b {
                        #clock-cells = <0>;
@@ -117,11 +131,20 @@
                        clock-output-names = "ostm0", "ostm1";
                };
 
+               mstp6_clks: mstp6_clks@fcfe042c {
+                       #clock-cells = <1>;
+                       compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+                       reg = <0xfcfe042c 4>;
+                       clocks = <&p0_clk>;
+                       clock-indices = <R7S72100_CLK_RTC>;
+                       clock-output-names = "rtc";
+               };
+
                mstp7_clks: mstp7_clks@fcfe0430 {
                        #clock-cells = <1>;
                        compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0xfcfe0430 4>;
-                       clocks = <&p0_clk>;
+                       clocks = <&b_clk>;
                        clock-indices = <R7S72100_CLK_ETHER>;
                        clock-output-names = "ether";
                };
@@ -162,9 +185,12 @@
                        #clock-cells = <1>;
                        compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0xfcfe0444 4>;
-                       clocks = <&p1_clk>, <&p1_clk>;
-                       clock-indices = <R7S72100_CLK_SDHI1 R7S72100_CLK_SDHI0>;
-                       clock-output-names = "sdhi1", "sdhi0";
+                       clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
+                       clock-indices = <
+                               R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
+                               R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
+                       >;
+                       clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
                };
        };
 
@@ -379,6 +405,13 @@
                cache-level = <2>;
        };
 
+       wdt: watchdog@fcfe0000 {
+               compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
+               reg = <0xfcfe0000 0x6>;
+               interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
+               clocks = <&p0_clk>;
+       };
+
        i2c0: i2c@fcfee000 {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -499,7 +532,10 @@
                              GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
                              GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 
-               clocks = <&mstp12_clks R7S72100_CLK_SDHI0>;
+               clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
+                        <&mstp12_clks R7S72100_CLK_SDHI01>;
+               clock-names = "core", "cd";
+               power-domains = <&cpg_clocks>;
                cap-sd-highspeed;
                cap-sdio-irq;
                status = "disabled";
@@ -512,7 +548,10 @@
                              GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
                              GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
 
-               clocks = <&mstp12_clks R7S72100_CLK_SDHI1>;
+               clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
+                        <&mstp12_clks R7S72100_CLK_SDHI11>;
+               clock-names = "core", "cd";
+               power-domains = <&cpg_clocks>;
                cap-sd-highspeed;
                cap-sdio-irq;
                status = "disabled";
@@ -535,4 +574,18 @@
                power-domains = <&cpg_clocks>;
                status = "disabled";
        };
+
+       rtc: rtc@fcff1000 {
+               compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
+               reg = <0xfcff1000 0x2e>;
+               interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING
+                             GIC_SPI 277 IRQ_TYPE_EDGE_RISING
+                             GIC_SPI 278 IRQ_TYPE_EDGE_RISING>;
+               interrupt-names = "alarm", "period", "carry";
+               clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
+                        <&rtc_x3_clk>, <&extal_clk>;
+               clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
+               power-domains = <&cpg_clocks>;
+               status = "disabled";
+       };
 };