Merge tag 'cramfs_fixes' of git://git.linaro.org/people/nicolas.pitre/linux

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / qcom-ipq4019.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 78db67337ed4a3ce90a8962f183444296c27fc53..2d56008d8d6b53e8a79f9f6265838a22484c5e73 100644 (file)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -52,78 +52,85 @@
                cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
-                       enable-method = "qcom,kpss-acc-v1";
+                       enable-method = "qcom,kpss-acc-v2";
+                       next-level-cache = <&L2>;
                        qcom,acc = <&acc0>;
                        qcom,saw = <&saw0>;
                        reg = <0x0>;
                        clocks = <&gcc GCC_APPS_CLK_SRC>;
                        clock-frequency = <0>;
-                       operating-points = <
-                               /* kHz  uV (fixed) */
-                               48000   1100000
-                               200000  1100000
-                               500000  1100000
-                               716000  1100000
-                       >;
                        clock-latency = <256000>;
+                       operating-points-v2 = <&cpu0_opp_table>;
                };
 
                cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
-                       enable-method = "qcom,kpss-acc-v1";
+                       enable-method = "qcom,kpss-acc-v2";
+                       next-level-cache = <&L2>;
                        qcom,acc = <&acc1>;
                        qcom,saw = <&saw1>;
                        reg = <0x1>;
                        clocks = <&gcc GCC_APPS_CLK_SRC>;
                        clock-frequency = <0>;
-                       operating-points = <
-                               /* kHz  uV (fixed) */
-                               48000   1100000
-                               200000  1100000
-                               500000  1100000
-                               666000  1100000
-                       >;
                        clock-latency = <256000>;
+                       operating-points-v2 = <&cpu0_opp_table>;
                };
 
                cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
-                       enable-method = "qcom,kpss-acc-v1";
+                       enable-method = "qcom,kpss-acc-v2";
+                       next-level-cache = <&L2>;
                        qcom,acc = <&acc2>;
                        qcom,saw = <&saw2>;
                        reg = <0x2>;
                        clocks = <&gcc GCC_APPS_CLK_SRC>;
                        clock-frequency = <0>;
-                       operating-points = <
-                               /* kHz  uV (fixed) */
-                               48000   1100000
-                               200000  1100000
-                               500000  1100000
-                               666000  1100000
-                       >;
                        clock-latency = <256000>;
+                       operating-points-v2 = <&cpu0_opp_table>;
                };
 
                cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
-                       enable-method = "qcom,kpss-acc-v1";
+                       enable-method = "qcom,kpss-acc-v2";
+                       next-level-cache = <&L2>;
                        qcom,acc = <&acc3>;
                        qcom,saw = <&saw3>;
                        reg = <0x3>;
                        clocks = <&gcc GCC_APPS_CLK_SRC>;
                        clock-frequency = <0>;
-                       operating-points = <
-                               /* kHz  uV (fixed) */
-                               48000   1100000
-                               200000  1100000
-                               500000  1100000
-                               666000  1100000
-                       >;
                        clock-latency = <256000>;
+                       operating-points-v2 = <&cpu0_opp_table>;
                };
+
+               L2: l2-cache {
+                       compatible = "cache";
+                       cache-level = <2>;
+               };
+       };
+
+       cpu0_opp_table: opp_table0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-48000000 {
+                       opp-hz = /bits/ 64 <48000000>;
+                       clock-latency-ns = <256000>;
+               };
+               opp-200000000 {
+                       opp-hz = /bits/ 64 <200000000>;
+                       clock-latency-ns = <256000>;
+               };
+               opp-500000000 {
+                       opp-hz = /bits/ 64 <500000000>;
+                       clock-latency-ns = <256000>;
+               };
+               opp-716000000 {
+                       opp-hz = /bits/ 64 <716000000>;
+                       clock-latency-ns = <256000>;
+               };
        };
 
        pmu {
@@ -291,49 +298,49 @@
                        status = "disabled";
                };
 
-                acc0: clock-controller@b088000 {
-                        compatible = "qcom,kpss-acc-v1";
-                        reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
-                };
+               acc0: clock-controller@b088000 {
+                       compatible = "qcom,kpss-acc-v2";
+                       reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
+               };
 
-                acc1: clock-controller@b098000 {
-                        compatible = "qcom,kpss-acc-v1";
-                        reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
-                };
+               acc1: clock-controller@b098000 {
+                       compatible = "qcom,kpss-acc-v2";
+                       reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
+               };
 
-                acc2: clock-controller@b0a8000 {
-                        compatible = "qcom,kpss-acc-v1";
-                        reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
-                };
+               acc2: clock-controller@b0a8000 {
+                       compatible = "qcom,kpss-acc-v2";
+                       reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
+               };
 
-                acc3: clock-controller@b0b8000 {
-                        compatible = "qcom,kpss-acc-v1";
-                        reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
-                };
+               acc3: clock-controller@b0b8000 {
+                       compatible = "qcom,kpss-acc-v2";
+                       reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
+               };
 
-                saw0: regulator@b089000 {
-                        compatible = "qcom,saw2";
-                        reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
+               saw0: regulator@b089000 {
+                       compatible = "qcom,saw2";
+                       reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
                         regulator;
-                };
+               };
 
-                saw1: regulator@b099000 {
-                        compatible = "qcom,saw2";
-                        reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
-                        regulator;
-                };
+               saw1: regulator@b099000 {
+                       compatible = "qcom,saw2";
+                       reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
+                       regulator;
+               };
 
-                saw2: regulator@b0a9000 {
-                        compatible = "qcom,saw2";
-                        reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
-                        regulator;
-                };
+               saw2: regulator@b0a9000 {
+                       compatible = "qcom,saw2";
+                       reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
+                       regulator;
+               };
 
-                saw3: regulator@b0b9000 {
-                        compatible = "qcom,saw2";
-                        reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
-                        regulator;
-                };
+               saw3: regulator@b0b9000 {
+                       compatible = "qcom,saw2";
+                       reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
+                       regulator;
+               };
 
                blsp1_uart1: serial@78af000 {
                        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
@@ -387,7 +394,7 @@
                        #size-cells = <2>;
 
                        ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
-                                 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
+                                 0x82000000 0 0x40300000 0x40300000 0 0x400000>;
 
                        interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
                        interrupt-names = "msi";