Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / meson8.dtsi

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index b98d44fde6b60bc9301a3b23cb65f2ccd0d8e64c..2d7a0752a460886de27f1a280169538f95422f9f 100644 (file)
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -45,6 +45,7 @@
 
 #include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8-gpio.h>
+#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
 #include "meson.dtsi"
 
 / {
@@ -60,6 +61,8 @@
                        compatible = "arm,cortex-a9";
                        next-level-cache = <&L2>;
                        reg = <0x200>;
+                       enable-method = "amlogic,meson8-smp";
+                       resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
                };
 
                cpu@201 {
@@ -67,6 +70,8 @@
                        compatible = "arm,cortex-a9";
                        next-level-cache = <&L2>;
                        reg = <0x201>;
+                       enable-method = "amlogic,meson8-smp";
+                       resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
                };
 
                cpu@202 {
@@ -74,6 +79,8 @@
                        compatible = "arm,cortex-a9";
                        next-level-cache = <&L2>;
                        reg = <0x202>;
+                       enable-method = "amlogic,meson8-smp";
+                       resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
                };
 
                cpu@203 {
@@ -81,6 +88,8 @@
                        compatible = "arm,cortex-a9";
                        next-level-cache = <&L2>;
                        reg = <0x203>;
+                       enable-method = "amlogic,meson8-smp";
+                       resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
                };
        };
 
@@ -118,6 +127,11 @@
 }; /* end of / */
 
 &aobus {
+       pmu: pmu@e0 {
+               compatible = "amlogic,meson8-pmu", "syscon";
+               reg = <0xe0 0x8>;
+       };
+
        pinctrl_aobus: pinctrl@84 {
                compatible = "amlogic,meson8-aobus-pinctrl";
                reg = <0x84 0xc>;
@@ -132,7 +146,7 @@
                        reg-names = "mux", "pull", "gpio";
                        gpio-controller;
                        #gpio-cells = <2>;
-                       gpio-ranges = <&pinctrl_aobus 0 120 16>;
+                       gpio-ranges = <&pinctrl_aobus 0 0 16>;
                };
 
                uart_ao_a_pins: uart_ao_a {
@@ -173,6 +187,11 @@
                reg = <0x8000 0x4>, <0x4000 0x460>;
        };
 
+       analog_top: analog-top@81a8 {
+               compatible = "amlogic,meson8-analog-top", "syscon";
+               reg = <0x81a8 0x14>;
+       };
+
        pwm_ef: pwm@86c0 {
                compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
                reg = <0x86c0 0x10>;
@@ -249,6 +268,19 @@
        };
 };
 
+&ahb_sram {
+       smp-sram@1ff80 {
+               compatible = "amlogic,meson8-smp-sram";
+               reg = <0x1ff80 0x8>;
+       };
+};
+
+&efuse {
+       compatible = "amlogic,meson8-efuse";
+       clocks = <&clkc CLKID_EFUSE>;
+       clock-names = "core";
+};
+
 &ethmac {
        clocks = <&clkc CLKID_ETH>;
        clock-names = "stmmaceth";
@@ -294,6 +326,12 @@
        clock-names = "clkin", "core", "sana";
 };
 
+&sdio {
+       compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
+       clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
+       clock-names = "core", "clkin";
+};
+
 &spifc {
        clocks = <&clkc CLKID_CLK81>;
 };