Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / lpc32xx.dtsi

diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 20b38f4ade375defa9c856cc0add75ade4158d09..7b7ec7b1217b89515b6c4455e1bc10538274d305 100644 (file)
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -1,14 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * NXP LPC32xx SoC
  *
+ * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
  * Copyright 2012 Roland Stigge <stigge@antcom.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
  */
 
 #include <dt-bindings/clock/lpc32xx-clock.h>
@@ -152,6 +147,7 @@
                        reg = <0x31060000 0x1000>;
                        interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk LPC32XX_CLK_MAC>;
+                       status = "disabled";
                };
 
                emc: memory-controller@31080000 {
@@ -185,6 +181,8 @@
                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clk LPC32XX_CLK_SSP0>;
                                clock-names = "apb_pclk";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
                                status = "disabled";
                        };
 
@@ -192,6 +190,8 @@
                                compatible = "nxp,lpc3220-spi";
                                reg = <0x20088000 0x1000>;
                                clocks = <&clk LPC32XX_CLK_SPI1>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
                                status = "disabled";
                        };
 
@@ -205,6 +205,8 @@
                                interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clk LPC32XX_CLK_SSP1>;
                                clock-names = "apb_pclk";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
                                status = "disabled";
                        };
 
@@ -212,12 +214,15 @@
                                compatible = "nxp,lpc3220-spi";
                                reg = <0x20090000 0x1000>;
                                clocks = <&clk LPC32XX_CLK_SPI2>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
                                status = "disabled";
                        };
 
                        i2s0: i2s@20094000 {
                                compatible = "nxp,lpc3220-i2s";
                                reg = <0x20094000 0x1000>;
+                               status = "disabled";
                        };
 
                        sd: sd@20098000 {
@@ -232,7 +237,8 @@
 
                        i2s1: i2s@2009c000 {
                                compatible = "nxp,lpc3220-i2s";
-                               reg = <0x2009C000 0x1000>;
+                               reg = <0x2009c000 0x1000>;
+                               status = "disabled";
                        };
 
                        /* UART5 first since it is the default console, ttyS0 */
@@ -275,7 +281,7 @@
 
                        i2c1: i2c@400a0000 {
                                compatible = "nxp,pnx-i2c";
-                               reg = <0x400A0000 0x100>;
+                               reg = <0x400a0000 0x100>;
                                interrupt-parent = <&sic1>;
                                interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
                                #address-cells = <1>;
@@ -286,7 +292,7 @@
 
                        i2c2: i2c@400a8000 {
                                compatible = "nxp,pnx-i2c";
-                               reg = <0x400A8000 0x100>;
+                               reg = <0x400a8000 0x100>;
                                interrupt-parent = <&sic1>;
                                interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
                                #address-cells = <1>;
@@ -297,7 +303,7 @@
 
                        mpwm: mpwm@400e8000 {
                                compatible = "nxp,lpc3220-motor-pwm";
-                               reg = <0x400E8000 0x78>;
+                               reg = <0x400e8000 0x78>;
                                status = "disabled";
                                #pwm-cells = <2>;
                        };
@@ -396,7 +402,7 @@
 
                        timer4: timer@4002c000 {
                                compatible = "nxp,lpc3220-timer";
-                               reg = <0x4002C000 0x1000>;
+                               reg = <0x4002c000 0x1000>;
                                interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
                                clocks = <&clk LPC32XX_CLK_TIMER4>;
                                clock-names = "timerclk";
@@ -414,7 +420,7 @@
 
                        watchdog: watchdog@4003c000 {
                                compatible = "nxp,pnx4008-wdt";
-                               reg = <0x4003C000 0x1000>;
+                               reg = <0x4003c000 0x1000>;
                                clocks = <&clk LPC32XX_CLK_WDOG>;
                        };
 
@@ -453,7 +459,7 @@
 
                        timer1: timer@4004c000 {
                                compatible = "nxp,lpc3220-timer";
-                               reg = <0x4004C000 0x1000>;
+                               reg = <0x4004c000 0x1000>;
                                interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
                                clocks = <&clk LPC32XX_CLK_TIMER1>;
                                clock-names = "timerclk";
@@ -479,7 +485,7 @@
 
                        pwm1: pwm@4005c000 {
                                compatible = "nxp,lpc3220-pwm";
-                               reg = <0x4005C000 0x4>;
+                               reg = <0x4005c000 0x4>;
                                clocks = <&clk LPC32XX_CLK_PWM1>;
                                assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
                                assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
@@ -488,7 +494,7 @@
 
                        pwm2: pwm@4005c004 {
                                compatible = "nxp,lpc3220-pwm";
-                               reg = <0x4005C004 0x4>;
+                               reg = <0x4005c004 0x4>;
                                clocks = <&clk LPC32XX_CLK_PWM2>;
                                assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
                                assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;