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Merge branch 'topic/fixes' into for-linus
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx7-colibri.dtsi
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index bb5bf94f1a3295f38ca5497a1e11e1a8646e1045..895fbde4d4333a3d5f37397feac66163911e4833 100644 (file)
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -43,7 +43,10 @@
 / {
        bl: backlight {
                compatible = "pwm-backlight";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_gpio_bl_on>;
                pwms = <&pwm1 0 5000000 0>;
+               enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
        };
 
        reg_module_3v3: regulator-module-3v3 {
@@ -86,7 +89,13 @@
 };
 
 &cpu0 {
-       arm-supply = <&reg_DCDC2>;
+       cpu-supply = <&reg_DCDC2>;
+};
+
+&ecspi3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
+       cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
 };
 
 &fec1 {
@@ -112,7 +121,6 @@
        fsl,use-minimum-ecc;
        nand-on-flash-bbt;
        nand-ecc-mode = "hw";
-       status = "okay";
 };
 
 &i2c1 {
@@ -299,6 +307,22 @@
        no-1-8-v;
        cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
        disable-wp;
+       vqmmc-supply = <&reg_LDO2>;
+};
+
+&usdhc3 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc3>;
+       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+       assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
+       assigned-clock-rates = <400000000>;
+       bus-width = <8>;
+       fsl,tuning-step = <2>;
+       max-frequency = <100000000>;
+       vmmc-supply = <&reg_module_3v3>;
+       vqmmc-supply = <&reg_DCDC3>;
+       non-removable;
 };
 
 &iomuxc {
@@ -307,17 +331,16 @@
 
        pinctrl_gpio1: gpio1-grp {
                fsl,pins = <
-                       MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3     0x14 /* SODIMM 55 */
-                       MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2     0x14 /* SODIMM 63 */
-                       MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0X14 /* SODIMM 73 */
-                       MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16       0X14 /* SODIMM 77 */
+                       MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3     0x74 /* SODIMM 55 */
+                       MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2     0x74 /* SODIMM 63 */
+                       MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16       0x14 /* SODIMM 77 */
                        MX7D_PAD_EPDC_DATA09__GPIO2_IO9         0x14 /* SODIMM 89 */
-                       MX7D_PAD_EPDC_DATA08__GPIO2_IO8         0x14 /* SODIMM 91 */
+                       MX7D_PAD_EPDC_DATA08__GPIO2_IO8         0x74 /* SODIMM 91 */
                        MX7D_PAD_LCD_RESET__GPIO3_IO4           0x14 /* SODIMM 93 */
                        MX7D_PAD_EPDC_DATA13__GPIO2_IO13        0x14 /* SODIMM 95 */
                        MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11    0x14 /* SODIMM 99 */
-                       MX7D_PAD_EPDC_DATA10__GPIO2_IO10        0x14 /* SODIMM 105 */
-                       MX7D_PAD_EPDC_DATA15__GPIO2_IO15        0x14 /* SODIMM 107 */
+                       MX7D_PAD_EPDC_DATA10__GPIO2_IO10        0x74 /* SODIMM 105 */
+                       MX7D_PAD_EPDC_DATA15__GPIO2_IO15        0x74 /* SODIMM 107 */
                        MX7D_PAD_EPDC_DATA00__GPIO2_IO0         0x14 /* SODIMM 111 */
                        MX7D_PAD_EPDC_DATA01__GPIO2_IO1         0x14 /* SODIMM 113 */
                        MX7D_PAD_EPDC_DATA02__GPIO2_IO2         0x14 /* SODIMM 115 */
@@ -329,11 +352,12 @@
                        MX7D_PAD_EPDC_SDCE2__GPIO2_IO22         0x14 /* SODIMM 127 */
                        MX7D_PAD_UART3_RTS_B__GPIO4_IO6         0x14 /* SODIMM 131 */
                        MX7D_PAD_EPDC_GDRL__GPIO2_IO26          0x14 /* SODIMM 133 */
+                       MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12       0x14 /* SODIMM 169 */
                        MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17       0x14 /* SODIMM 24 */
                        MX7D_PAD_SD2_DATA2__GPIO5_IO16          0x14 /* SODIMM 100 */
                        MX7D_PAD_SD2_DATA3__GPIO5_IO17          0x14 /* SODIMM 102 */
                        MX7D_PAD_EPDC_GDSP__GPIO2_IO27          0x14 /* SODIMM 104 */
-                       MX7D_PAD_EPDC_BDR0__GPIO2_IO28          0x14 /* SODIMM 106 */
+                       MX7D_PAD_EPDC_BDR0__GPIO2_IO28          0x74 /* SODIMM 106 */
                        MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x14 /* SODIMM 110 */
                        MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30       0x14 /* SODIMM 112 */
                        MX7D_PAD_EPDC_SDCLK__GPIO2_IO16         0x14 /* SODIMM 114 */
@@ -357,8 +381,7 @@
        pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */
                fsl,pins = <
                        MX7D_PAD_ECSPI2_SS0__GPIO4_IO23         0x14 /* SODIMM 65 */
-                       MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x14 /* SODIMM 69 */
-                       MX7D_PAD_SD1_WP__GPIO5_IO1              0x14 /* SODIMM 71 */
+                       MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x74 /* SODIMM 69 */
                        MX7D_PAD_I2C4_SDA__GPIO4_IO15           0x14 /* SODIMM 75 */
                        MX7D_PAD_ECSPI1_MISO__GPIO4_IO18        0x14 /* SODIMM 79 */
                        MX7D_PAD_I2C3_SCL__GPIO4_IO12           0x14 /* SODIMM 81 */
@@ -378,8 +401,8 @@
                        MX7D_PAD_LCD_DATA19__GPIO3_IO24         0x14 /* SODIMM 138 */
                        MX7D_PAD_LCD_DATA20__GPIO3_IO25         0x14 /* SODIMM 140 */
                        MX7D_PAD_LCD_DATA21__GPIO3_IO26         0x14 /* SODIMM 142 */
-                       MX7D_PAD_LCD_DATA22__GPIO3_IO27         0x14 /* SODIMM 146 */
-                       MX7D_PAD_LCD_DATA23__GPIO3_IO28         0x14 /* SODIMM 148 */
+                       MX7D_PAD_LCD_DATA22__GPIO3_IO27         0x74 /* SODIMM 144 */
+                       MX7D_PAD_LCD_DATA23__GPIO3_IO28         0x74 /* SODIMM 146 */
                >;
        };
 
@@ -396,6 +419,12 @@
                >;
        };
 
+       pinctrl_can_int: can-int-grp {
+               fsl,pins = <
+                       MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0X14 /* SODIMM 73 */
+               >;
+       };
+
        pinctrl_enet1: enet1grp {
                fsl,pins = <
                        MX7D_PAD_ENET1_CRS__GPIO7_IO14                  0x14
@@ -434,12 +463,17 @@
                >;
        };
 
+       pinctrl_gpio_bl_on: gpio-bl-on {
+               fsl,pins = <
+                       MX7D_PAD_SD1_WP__GPIO5_IO1              0x14 /* SODIMM 71 */
+               >;
+       };
+
        pinctrl_gpmi_nand: gpmi-nand-grp {
                fsl,pins = <
                        MX7D_PAD_SD3_CLK__NAND_CLE              0x71
                        MX7D_PAD_SD3_CMD__NAND_ALE              0x71
                        MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B       0x71
-                       MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B       0x71
                        MX7D_PAD_SAI1_TX_DATA__NAND_READY_B     0x74
                        MX7D_PAD_SD3_STROBE__NAND_RE_B          0x71
                        MX7D_PAD_SD3_RESET_B__NAND_WE_B         0x71
@@ -507,6 +541,7 @@
        pinctrl_pwm1: pwm1-grp {
                fsl,pins = <
                        MX7D_PAD_GPIO1_IO08__PWM1_OUT           0x79
+                       MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x4
                >;
        };
 
@@ -525,6 +560,7 @@
        pinctrl_pwm4: pwm4-grp {
                fsl,pins = <
                        MX7D_PAD_GPIO1_IO11__PWM4_OUT           0x79
+                       MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20        0x4
                >;
        };
 
@@ -559,7 +595,7 @@
                >;
        };
 
-       pinctrl_usbotg2_reg: gpio-usbotg2-vbus {
+       pinctrl_usbh_reg: gpio-usbh-vbus {
                fsl,pins = <
                        MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */
                >;
@@ -576,6 +612,54 @@
                >;
        };
 
+       pinctrl_usdhc3: usdhc3grp {
+               fsl,pins = <
+                       MX7D_PAD_SD3_CMD__SD3_CMD               0x59
+                       MX7D_PAD_SD3_CLK__SD3_CLK               0x19
+                       MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
+                       MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
+                       MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
+                       MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
+                       MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
+                       MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
+                       MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
+                       MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
+                       MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
+               >;
+       };
+
+       pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+               fsl,pins = <
+                       MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
+                       MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
+                       MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
+                       MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
+                       MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
+                       MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
+                       MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
+                       MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
+                       MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
+                       MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
+                       MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
+               >;
+       };
+
+       pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+               fsl,pins = <
+                       MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
+                       MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
+                       MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
+                       MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
+                       MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
+                       MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
+                       MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
+                       MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
+                       MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
+                       MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
+                       MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
+               >;
+       };
+
        pinctrl_sai1: sai1-grp {
                fsl,pins = <
                        MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK     0x1f
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