Merge tag 'pci-v4.16-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx6qdl-udoo.dtsi

diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
index c96c91d83678511478650b87afaeb33a7e0f9f40..4161b7d4323a30da02076c791d5201d3cc19dc2c 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
@@ -28,6 +28,13 @@
                status = "disabled";
        };
 
+       gpio-poweroff {
+               compatible = "gpio-poweroff";
+               gpios = <&gpio2 4 0>;
+               pinctrl-0 = <&pinctrl_power_off>;
+               pinctrl-names = "default";
+       };
+
        memory {
                reg = <0x10000000 0x40000000>;
        };
@@ -172,6 +179,12 @@
                        >;
                };
 
+               pinctrl_power_off: poweroffgrp {
+                       fsl,pins = <
+                               MX6QDL_PAD_NANDF_D4__GPIO2_IO04         0x30
+                       >;
+               };
+
                pinctrl_touchscreenp7: touchscreenp7grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD2_DAT0__GPIO1_IO15         0x70
@@ -208,8 +221,8 @@
                        fsl,pins = <
                                MX6QDL_PAD_DI0_PIN2__AUD6_TXD           0x1b0b0
                                MX6QDL_PAD_DI0_PIN3__AUD6_TXFS          0x1b0b0
-                               MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x1b0b0
-                               MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x1b0b0
+                               MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x13080
+                               MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x13080
                                MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b0
                        >;
                };
@@ -218,8 +231,8 @@
                        fsl,pins = <
                                MX6QDL_PAD_DI0_PIN2__AUD6_TXD           0x1b0b0
                                MX6QDL_PAD_DI0_PIN3__GPIO4_IO19         0x1b0b0
-                               MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x1b0b0
-                               MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x1b0b0
+                               MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x13080
+                               MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x13080
                                MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b0
                        >;
                };
@@ -228,8 +241,8 @@
                        fsl,pins = <
                                MX6QDL_PAD_DI0_PIN2__GPIO4_IO18         0x1b0b0
                                MX6QDL_PAD_DI0_PIN3__GPIO4_IO19         0x1b0b0
-                               MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x1b0b0
-                               MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x1b0b0
+                               MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x13080
+                               MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x13080
                                MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b0
                        >;
                };