Merge branch 'work.cramfs' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx6qdl-icore-rqs.dtsi

diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
index 7ca291e9dbdb234b253d09b72fd1cb2a3f5aac71..b6220d62f6de0f48f2ba667f237d90e987f1bcf7 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
@@ -41,6 +41,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/clock/imx6qdl-clock.h>
+#include <dt-bindings/sound/fsl-imx-audmux.h>
 
 / {
        memory {
@@ -118,17 +119,77 @@
                clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>;
                clock-names = "refclk";
        };
-};
 
-&clks {
-       assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
-       assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
+       sound {
+               compatible = "simple-audio-card";
+               simple-audio-card,name = "imx6qdl-icore-rqs-sgtl5000";
+               simple-audio-card,format = "i2s";
+               simple-audio-card,bitclock-master = <&dailink_master>;
+               simple-audio-card,frame-master = <&dailink_master>;
+               simple-audio-card,widgets =
+                       "Microphone", "Mic Jack",
+                       "Headphone", "Headphone Jack",
+                       "Line", "Line In Jack",
+                       "Speaker", "Line Out Jack",
+                       "Speaker", "Ext Spk";
+               simple-audio-card,routing =
+                       "MIC_IN", "Mic Jack",
+                       "Mic Jack", "Mic Bias",
+                       "Headphone Jack", "HP_OUT";
+
+               simple-audio-card,cpu {
+                       sound-dai = <&ssi1>;
+               };
+
+               dailink_master: simple-audio-card,codec {
+                       sound-dai = <&sgtl5000>;
+               };
+       };
 };
 
 &audmux {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_audmux>;
        status = "okay";
+
+       audmux_ssi1 {
+               fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
+               fsl,port-config = <
+                       (IMX_AUDMUX_V2_PTCR_TFSDIR |
+                       IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
+                       IMX_AUDMUX_V2_PTCR_TCLKDIR |
+                       IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
+                       IMX_AUDMUX_V2_PTCR_SYN)
+                       IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
+               >;
+       };
+
+       audmux_aud4 {
+               fsl,audmux-port = <MX51_AUDMUX_PORT4>;
+               fsl,port-config = <
+                       IMX_AUDMUX_V2_PTCR_SYN
+                       IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
+               >;
+       };
+};
+
+&can1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_can1>;
+       xceiver-supply = <&reg_3p3v>;
+       status = "okay";
+};
+
+&can2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_can2>;
+       xceiver-supply = <&reg_3p3v>;
+       status = "okay";
+};
+
+&clks {
+       assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
+       assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
 };
 
 &fec {
@@ -174,6 +235,16 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c3>;
        status = "okay";
+
+       sgtl5000: codec@a {
+               #sound-dai-cells = <0>;
+               compatible = "fsl,sgtl5000";
+               reg = <0x0a>;
+               clocks = <&clks IMX6QDL_CLK_CKO>;
+               VDDA-supply = <&reg_2p5v>;
+               VDDIO-supply = <&reg_3p3v>;
+               VDDD-supply = <&reg_1p8v>;
+       };
 };
 
 &pcie {
@@ -184,6 +255,7 @@
 };
 
 &ssi1 {
+       fsl,mode = "i2s-slave";
        status = "okay";
 };
 
@@ -270,6 +342,20 @@
                >;
        };
 
+       pinctrl_can1: can1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
+                       MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
+               >;
+       };
+
+       pinctrl_can2: can2grp {
+               fsl,pins = <
+                       MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
+                       MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
+               >;
+       };
+
        pinctrl_i2c1: i2c1grp {
                fsl,pins = <
                        MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1