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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx6qdl-gw552x.dtsi
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
index 67613dd7cc926fa6d11c273dadfb1c8314365ad1..c67c106050705bc2879e62ee9a8048339de3068e 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -270,105 +270,103 @@
 };
 
 &iomuxc {
-       imx6qdl-gw552x {
-               pinctrl_gpio_leds: gpioledsgrp {
-                       fsl,pins = <
-                               MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
-                               MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
-                               MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
-                       >;
-               };
+       pinctrl_gpio_leds: gpioledsgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
+                       MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
+                       MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
+               >;
+       };
 
-               pinctrl_gpmi_nand: gpminandgrp {
-                       fsl,pins = <
-                               MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
-                               MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
-                               MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
-                               MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
-                               MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
-                               MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
-                               MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
-                               MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
-                               MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
-                               MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
-                               MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
-                               MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
-                               MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
-                               MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
-                               MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
-                       >;
-               };
+       pinctrl_gpmi_nand: gpminandgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
+                       MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
+                       MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
+                       MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
+                       MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
+                       MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
+                       MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
+                       MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
+                       MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
+                       MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
+                       MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
+                       MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
+                       MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
+                       MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
+                       MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
+               >;
+       };
 
-               pinctrl_i2c1: i2c1grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
-                               MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
-                       >;
-               };
+       pinctrl_i2c1: i2c1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                       MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+               >;
+       };
 
-               pinctrl_i2c2: i2c2grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
-                               MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
-                       >;
-               };
+       pinctrl_i2c2: i2c2grp {
+               fsl,pins = <
+                       MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                       MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+               >;
+       };
 
-               pinctrl_i2c3: i2c3grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
-                               MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
-                       >;
-               };
+       pinctrl_i2c3: i2c3grp {
+               fsl,pins = <
+                       MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
+                       MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
+               >;
+       };
 
-               pinctrl_pcie: pciegrp {
-                       fsl,pins = <
-                               MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0
-                       >;
-               };
+       pinctrl_pcie: pciegrp {
+               fsl,pins = <
+                       MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0
+               >;
+       };
 
-               pinctrl_pmic: pmicgrp {
-                       fsl,pins = <
-                               MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
-                       >;
-               };
+       pinctrl_pmic: pmicgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
+               >;
+       };
 
-               pinctrl_pwm2: pwm2grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
-                       >;
-               };
+       pinctrl_pwm2: pwm2grp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
+               >;
+       };
 
-               pinctrl_pwm3: pwm3grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
-                       >;
-               };
+       pinctrl_pwm3: pwm3grp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
+               >;
+       };
 
-               pinctrl_uart2: uart2grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
-                               MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
-                       >;
-               };
+       pinctrl_uart2: uart2grp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
+                       MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
+               >;
+       };
 
-               pinctrl_uart3: uart3grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
-                               MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
-                       >;
-               };
+       pinctrl_uart3: uart3grp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
+                       MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
+               >;
+       };
 
-               pinctrl_uart5: uart5grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
-                               MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
-                       >;
-               };
+       pinctrl_uart5: uart5grp {
+               fsl,pins = <
+                       MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
+                       MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
+               >;
+       };
 
-               pinctrl_wdog: wdoggrp {
-                       fsl,pins = <
-                               MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
-                       >;
-               };
+       pinctrl_wdog: wdoggrp {
+               fsl,pins = <
+                       MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
+               >;
        };
 };
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