Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx6qdl-gw54xx.dtsi
index 81b2fcf6eedfb23c79499ca78160d5092625e989..e4d1c5250d1edfd9be5d06b83fa6c58846c0783a 100644 (file)
@@ -10,6 +10,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/fsl-imx-audmux.h>
 
 / {
        /* these are used by bootloader for disabling nodes */
                };
        };
 
-       sound {
+       sound-analog {
                compatible = "fsl,imx6q-ventana-sgtl5000",
                             "fsl,imx-audio-sgtl5000";
                model = "sgtl5000-audio";
                ssi-controller = <&ssi1>;
-               audio-codec = <&codec>;
+               audio-codec = <&sgtl5000>;
                audio-routing =
                        "MIC_IN", "Mic Jack",
                        "Mic Jack", "Mic Bias",
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
        status = "okay";
+
+       ssi2 {
+               fsl,audmux-port = <1>;
+               fsl,port-config = <
+                       (IMX_AUDMUX_V2_PTCR_TFSDIR |
+                       IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
+                       IMX_AUDMUX_V2_PTCR_TCLKDIR |
+                       IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
+                       IMX_AUDMUX_V2_PTCR_SYN)
+                       IMX_AUDMUX_V2_PDCR_RXDSEL(4)
+               >;
+       };
+
+       aud5 {
+               fsl,audmux-port = <4>;
+               fsl,port-config = <
+                       IMX_AUDMUX_V2_PTCR_SYN
+                       IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
+       };
 };
 
 &can1 {
        pinctrl-0 = <&pinctrl_i2c3>;
        status = "okay";
 
-       codec: sgtl5000@a {
+       sgtl5000: audio-codec@a {
                compatible = "fsl,sgtl5000";
                reg = <0x0a>;
                clocks = <&clks IMX6QDL_CLK_CKO>;
                        MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
                        MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
                        MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* AUD4_MCK */
+                       MX6QDL_PAD_EIM_D25__AUD5_RXC            0x130b0
+                       MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
+                       MX6QDL_PAD_EIM_D24__AUD5_RXFS           0x130b0
                >;
        };