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Merge tag 'for-linus-20171120' of git://git.infradead.org/linux-mtd
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx6q-gw5400-a.dts
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index 9dbeea05a9495f6fc2b5e56b55659508ca1230df..29adaa7c72f84cc4efb327df156f8af584337491 100644 (file)
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -211,7 +211,7 @@
        pinctrl-0 = <&pinctrl_i2c2>;
        status = "okay";
 
-       pmic: pfuze100@08 {
+       pmic: pfuze100@8 {
                compatible = "fsl,pfuze100";
                reg = <0x08>;
 
@@ -322,7 +322,7 @@
                reg = <0x1c>;
        };
 
-       codec: sgtl5000@0a {
+       codec: sgtl5000@a {
                compatible = "fsl,sgtl5000";
                reg = <0x0a>;
                clocks = <&clks IMX6QDL_CLK_CKO>;
@@ -330,7 +330,7 @@
                VDDIO-supply = <&reg_3p3v>;
        };
 
-       touchscreen: egalax_ts@04 {
+       touchscreen: egalax_ts@4 {
                compatible = "eeti,egalax_ts";
                reg = <0x04>;
                interrupt-parent = <&gpio7>;
@@ -392,127 +392,124 @@
 };
 
 &iomuxc {
-       imx6q-gw5400-a {
-
-               pinctrl_audmux: audmuxgrp {
-                       fsl,pins = <
-                               MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
-                               MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
-                               MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
-                               MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
-                               MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* AUD4_MCK */
-                       >;
-               };
+       pinctrl_audmux: audmuxgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
+                       MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
+                       MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
+                       MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
+                       MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* AUD4_MCK */
+               >;
+       };
 
-               pinctrl_ecspi1: ecspi1grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
-                               MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
-                               MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
-                               MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x1b0b0 /* SPINOR_CS0# */
-                       >;
-               };
+       pinctrl_ecspi1: ecspi1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
+                       MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
+                       MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
+                       MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x1b0b0 /* SPINOR_CS0# */
+               >;
+       };
 
-               pinctrl_enet: enetgrp {
-                       fsl,pins = <
-                               MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
-                               MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
-                               MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
-                               MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
-                               MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
-                               MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
-                               MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
-                               MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
-                               MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
-                               MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
-                               MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
-                               MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
-                               MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
-                               MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
-                               MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
-                               MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
-                       >;
-               };
+       pinctrl_enet: enetgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
+                       MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
+                       MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
+                       MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
+                       MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
+                       MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
+                       MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
+                       MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
+                       MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
+                       MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
+                       MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
+                       MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
+                       MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                       MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                       MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                       MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+               >;
+       };
 
-               pinctrl_gpio_leds: gpioledsgrp {
-                       fsl,pins = <
-                               MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0 /* user1 led */
-                               MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x1b0b0 /* user2 led */
-                               MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0 /* user3 led */
-                       >;
-               };
+       pinctrl_gpio_leds: gpioledsgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0 /* user1 led */
+                       MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x1b0b0 /* user2 led */
+                       MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0 /* user3 led */
+               >;
+       };
 
-               pinctrl_i2c1: i2c1grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
-                               MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
-                       >;
-               };
+       pinctrl_i2c1: i2c1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                       MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+               >;
+       };
 
-               pinctrl_i2c2: i2c2grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
-                               MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
-                       >;
-               };
+       pinctrl_i2c2: i2c2grp {
+               fsl,pins = <
+                       MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                       MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+               >;
+       };
 
-               pinctrl_i2c3: i2c3grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
-                               MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
-                       >;
-               };
+       pinctrl_i2c3: i2c3grp {
+               fsl,pins = <
+                       MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
+                       MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
+               >;
+       };
 
-               pinctrl_pcie: pciegrp {
-                       fsl,pins = <
-                               MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x1b0b0 /* PCIE IRQ */
-                               MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0 /* PCIE RST */
-                       >;
-               };
+       pinctrl_pcie: pciegrp {
+               fsl,pins = <
+                       MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x1b0b0 /* PCIE IRQ */
+                       MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0 /* PCIE RST */
+               >;
+       };
 
-               pinctrl_pps: ppsgrp {
-                       fsl,pins = <
-                               MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x1b0b0 /* GPS_PPS */
-                       >;
-               };
+       pinctrl_pps: ppsgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x1b0b0 /* GPS_PPS */
+               >;
+       };
 
-               pinctrl_uart1: uart1grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
-                               MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
-                       >;
-               };
+       pinctrl_uart1: uart1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
+                       MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
+               >;
+       };
 
-               pinctrl_uart2: uart2grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
-                               MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
-                       >;
-               };
+       pinctrl_uart2: uart2grp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
+                       MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
+               >;
+       };
 
-               pinctrl_uart5: uart5grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
-                               MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
-                       >;
-               };
+       pinctrl_uart5: uart5grp {
+               fsl,pins = <
+                       MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
+                       MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
+               >;
+       };
 
-               pinctrl_usbotg: usbotggrp {
-                       fsl,pins = <
-                               MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
-                               MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* OTG_PWR_EN */
-                       >;
-               };
+       pinctrl_usbotg: usbotggrp {
+               fsl,pins = <
+                       MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                       MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* OTG_PWR_EN */
+               >;
+       };
 
-               pinctrl_usdhc3: usdhc3grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
-                               MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
-                               MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
-                               MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
-                               MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
-                               MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
-                       >;
-               };
+       pinctrl_usdhc3: usdhc3grp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                       MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+               >;
        };
 };
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