Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx6q-gw53xx.dts

diff --git a/arch/arm/boot/dts/imx6q-gw53xx.dts b/arch/arm/boot/dts/imx6q-gw53xx.dts
index d76aaa83dad070ade4861a599dee1168da69c5cf..a56ef77eff3f9fb0aa2706aa027825311d14dece 100644 (file)
--- a/arch/arm/boot/dts/imx6q-gw53xx.dts
+++ b/arch/arm/boot/dts/imx6q-gw53xx.dts
@@ -18,6 +18,64 @@
        compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q";
 };
 
+&i2c3 {
+       adv7180: camera@20 {
+               compatible = "adi,adv7180";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_adv7180>;
+               reg = <0x20>;
+               powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+               interrupt-parent = <&gpio3>;
+               interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+
+               port {
+                       adv7180_to_ipu2_csi1_mux: endpoint {
+                               remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
+                               bus-width = <8>;
+                       };
+               };
+       };
+};
+
+&ipu2_csi1_from_ipu2_csi1_mux {
+       bus-width = <8>;
+};
+
+&ipu2_csi1_mux_from_parallel_sensor {
+       remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
+       bus-width = <8>;
+};
+
+&ipu2_csi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ipu2_csi1>;
+};
+
 &sata {
        status = "okay";
 };
+
+&iomuxc {
+       pinctrl_adv7180: adv7180grp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x0001b0b0
+                       MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x4001b0b0
+               >;
+       };
+
+       pinctrl_ipu2_csi1: ipu2_csi1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19    0x1b0b0
+                       MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18    0x1b0b0
+                       MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17    0x1b0b0
+                       MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16    0x1b0b0
+                       MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15    0x1b0b0
+                       MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14    0x1b0b0
+                       MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13    0x1b0b0
+                       MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12    0x1b0b0
+                       MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC     0x1b0b0
+                       MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC     0x1b0b0
+                       MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK    0x1b0b0
+               >;
+       };
+};