Merge branch 'i2c-mux/for-next' of https://github.com/peda-r/i2c-mux into i2c/for-5.2

[sfrench/cifs-2.6.git] / arch / arc / plat-eznps / Kconfig

diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index 8eff057efcaebeae04b1fb801c003418090551eb..2eaecfb063a7336f2a78c54e31ab09f2576c63f6 100644 (file)
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -26,8 +26,8 @@ config EZNPS_MTM_EXT
        help
          Here we add new hierarchy for CPUs topology.
          We got:
-               Core
-               Thread
+           Core
+           Thread
          At the new thread level each CPU represent one HW thread.
          At highest hierarchy each core contain 16 threads,
          any of them seem like CPU from Linux point of view.
@@ -35,10 +35,10 @@ config EZNPS_MTM_EXT
          core and HW scheduler round robin between them.
 
 config EZNPS_MEM_ERROR_ALIGN
-       bool "ARC-EZchip Memory error as an exception"
-       depends on EZNPS_MTM_EXT
-       default n
-       help
+       bool "ARC-EZchip Memory error as an exception"
+       depends on EZNPS_MTM_EXT
+       default n
+       help
          On the real chip of the NPS, user memory errors are handled
          as a machine check exception, which is fatal, whereas on
          simulator platform for NPS, is handled as a Level 2 interrupt