trivial: fix typos s/paramter/parameter/ and s/excute/execute/ in documentation and...

[sfrench/cifs-2.6.git] / Documentation / powerpc / dts-bindings / fsl / board.txt

diff --git a/Documentation/powerpc/dts-bindings/fsl/board.txt b/Documentation/powerpc/dts-bindings/fsl/board.txt
index 81a917ef96e9afbeb609fd6984f8f0eaa1b316d2..e8b5bc24d0acab21dd1efd094fc8940cf7c0b63a 100644 (file)
--- a/Documentation/powerpc/dts-bindings/fsl/board.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/board.txt
@@ -18,7 +18,7 @@ This is the memory-mapped registers for on board FPGA.
 
 Required properities:
 - compatible : should be "fsl,fpga-pixis".
-- reg : should contain the address and the lenght of the FPPGA register
+- reg : should contain the address and the length of the FPPGA register
   set.
 
 Example (MPC8610HPCD):
@@ -27,3 +27,33 @@ Example (MPC8610HPCD):
                compatible = "fsl,fpga-pixis";
                reg = <0xe8000000 32>;
        };
+
+* Freescale BCSR GPIO banks
+
+Some BCSR registers act as simple GPIO controllers, each such
+register can be represented by the gpio-controller node.
+
+Required properities:
+- compatible : Should be "fsl,<board>-bcsr-gpio".
+- reg : Should contain the address and the length of the GPIO bank
+  register.
+- #gpio-cells : Should be two. The first cell is the pin number and the
+  second cell is used to specify optional parameters (currently unused).
+- gpio-controller : Marks the port as GPIO controller.
+
+Example:
+
+       bcsr@1,0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "fsl,mpc8360mds-bcsr";
+               reg = <1 0 0x8000>;
+               ranges = <0 1 0 0x8000>;
+
+               bcsr13: gpio-controller@d {
+                       #gpio-cells = <2>;
+                       compatible = "fsl,mpc8360mds-bcsr-gpio";
+                       reg = <0xd 1>;
+                       gpio-controller;
+               };
+       };