Merge tag 'drm-msm-fixes-2019-01-24' of git://people.freedesktop.org/~robclark/linux...

[sfrench/cifs-2.6.git] / Documentation / devicetree / bindings / phy / qcom-qmp-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
index fbc198d5dd39eaee1838a37368a7c8025938f530..41a1074228ba7df7a626425814104698aedf647c 100644 (file)
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -25,10 +25,6 @@ Required properties:
   - For all others:
     - The reg-names property shouldn't be defined.
 
- - #clock-cells: must be 1
-    - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
-      interface (for pipe based PHYs). These clock are then gate-controlled
-      by gcc.
  - #address-cells: must be 1
  - #size-cells: must be 1
  - ranges: must be present
@@ -82,27 +78,33 @@ Required nodes:
  - Each device node of QMP phy is required to have as many child nodes as
    the number of lanes the PHY has.
 
-Required properties for child node:
+Required properties for child nodes of PCIe PHYs (one child per lane):
  - reg: list of offset and length pairs of register sets for PHY blocks -
-       - index 0: tx
-       - index 1: rx
-       - index 2: pcs
-       - index 3: pcs_misc (optional)
+       tx, rx, pcs, and pcs_misc (optional).
+ - #phy-cells: must be 0
 
+Required properties for a single "lanes" child node of non-PCIe PHYs:
+ - reg: list of offset and length pairs of register sets for PHY blocks
+       For 1-lane devices:
+               tx, rx, pcs, and (optionally) pcs_misc
+       For 2-lane devices:
+               tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc
  - #phy-cells: must be 0
 
-Required properties child node of pcie and usb3 qmp phys:
+Required properties for child node of PCIe and USB3 qmp phys:
  - clocks: a list of phandles and clock-specifier pairs,
           one for each entry in clock-names.
  - clock-names: Must contain following:
                 "pipe<lane-number>" for pipe clock specific to each lane.
  - clock-output-names: Name of the PHY clock that will be the parent for
                       the above pipe clock.
-
        For "qcom,ipq8074-qmp-pcie-phy":
                - "pcie20_phy0_pipe_clk"        Pipe Clock parent
                        (or)
                  "pcie20_phy1_pipe_clk"
+ - #clock-cells: must be 0
+    - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then
+      gate-controlled by the gcc.
 
 Required properties for child node of PHYs with lane reset, AKA:
        "qcom,msm8996-qmp-pcie-phy"
@@ -115,7 +117,6 @@ Example:
        phy@34000 {
                compatible = "qcom,msm8996-qmp-pcie-phy";
                reg = <0x34000 0x488>;
-               #clock-cells = <1>;
                #address-cells = <1>;
                #size-cells = <1>;
                ranges;
@@ -137,6 +138,7 @@ Example:
                        reg = <0x35000 0x130>,
                                <0x35200 0x200>,
                                <0x35400 0x1dc>;
+                       #clock-cells = <0>;
                        #phy-cells = <0>;
 
                        clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
@@ -150,3 +152,54 @@ Example:
                ...
                ...
        };
+
+       phy@88eb000 {
+               compatible = "qcom,sdm845-qmp-usb3-uni-phy";
+               reg = <0x88eb000 0x18c>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+                        <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+                        <&gcc GCC_USB3_SEC_CLKREF_CLK>,
+                        <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
+               clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+
+               resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
+                        <&gcc GCC_USB3_PHY_SEC_BCR>;
+               reset-names = "phy", "common";
+
+               lane@88eb200 {
+                       reg = <0x88eb200 0x128>,
+                             <0x88eb400 0x1fc>,
+                             <0x88eb800 0x218>,
+                             <0x88eb600 0x70>;
+                       #clock-cells = <0>;
+                       #phy-cells = <0>;
+                       clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+                       clock-names = "pipe0";
+                       clock-output-names = "usb3_uni_phy_pipe_clk_src";
+               };
+       };
+
+       phy@1d87000 {
+               compatible = "qcom,sdm845-qmp-ufs-phy";
+               reg = <0x1d87000 0x18c>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+               clock-names = "ref",
+                             "ref_aux";
+               clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
+                        <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+               lanes@1d87400 {
+                       reg = <0x1d87400 0x108>,
+                             <0x1d87600 0x1e0>,
+                             <0x1d87c00 0x1dc>,
+                             <0x1d87800 0x108>,
+                             <0x1d87a00 0x1e0>;
+                       #phy-cells = <0>;
+               };
+       };