Merge branch 'core-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...

[sfrench/cifs-2.6.git] / Documentation / devicetree / bindings / pci / fsl,imx6q-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index d514c1f2365f59ab04c586b4cd69f52349c80cbe..a7f5f5afa0e6798330a8f46ad88abb05e6524052 100644 (file)
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -9,6 +9,7 @@ Required properties:
        - "fsl,imx6sx-pcie",
        - "fsl,imx6qp-pcie"
        - "fsl,imx7d-pcie"
+       - "fsl,imx8mq-pcie"
 - reg: base address and length of the PCIe controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
@@ -45,7 +46,7 @@ Additional required properties for imx6sx-pcie:
   PCIE_PHY power domains
 - power-domain-names: Must be "pcie", "pcie_phy"
 
-Additional required properties for imx7d-pcie:
+Additional required properties for imx7d-pcie and imx8mq-pcie:
 - power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
 - resets: Must contain phandles to PCIe-related reset lines exposed by SRC
   IP block
@@ -53,6 +54,11 @@ Additional required properties for imx7d-pcie:
               - "pciephy"
               - "apps"
               - "turnoff"
+- fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node.
+
+Additional required properties for imx8mq-pcie:
+- clock-names: Must include the following additional entries:
+       - "pcie_aux"
 
 Example:
 
@@ -79,3 +85,13 @@ Example:
                clocks = <&clks 144>, <&clks 206>, <&clks 189>;
                clock-names = "pcie", "pcie_bus", "pcie_phy";
        };
+
+* Freescale i.MX7d PCIe PHY
+
+This is the PHY associated with the IMX7d PCIe controller.  It's used by the
+PCI-e controller via the fsl,imx7d-pcie-phy phandle.
+
+Required properties:
+- compatible:
+       - "fsl,imx7d-pcie-phy"
+- reg: base address and length of the PCIe PHY controller