* Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
+This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service)
+IP block. The IP supports multiple options for bus type, clocking and reset
+structure, and feature list. Consequently, a number of properties and list
+entries in properties are marked as optional, or only required in specific HW
+configurations.
Required properties:
-- compatible: Should be "snps,dwc-qos-ethernet-4.10"
+- compatible: One of:
+ - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
+ Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
+ - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
+ Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
+ - "snps,dwc-qos-ethernet-4.10"
+ This combination is deprecated. It should be treated as equivalent to
+ "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
+ compatible with earlier revisions of this binding.
- reg: Address and length of the register set for the device
-- clocks: Phandles to the reference clock and the bus clock
-- clock-names: Should be "phy_ref_clk" for the reference clock and "apb_pclk"
- for the bus clock.
+- clocks: Phandle and clock specifiers for each entry in clock-names, in the
+ same order. See ../clock/clock-bindings.txt.
+- clock-names: May contain any/all of the following depending on the IP
+ configuration, in any order:
+ - "tx"
+ The EQOS transmit path clock. The HW signal name is clk_tx_i.
+ In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
+ path. In other configurations, other clocks (such as tx_125, rmii) may
+ drive the PHY TX path.
+ - "rx"
+ The EQOS receive path clock. The HW signal name is clk_rx_i.
+ In some configurations (e.g. GMII/RGMII), this clock is derived from the
+ PHY's RX clock output. In other configurations, other clocks (such as
+ rx_125, rmii) may drive the EQOS RX path.
+ In cases where the PHY clock is directly fed into the EQOS receive path
+ without intervening logic, the DT need not represent this clock, since it
+ is assumed to be fully under the control of the PHY device/driver. In
+ cases where SoC integration adds additional logic to this path, such as a
+ SW-controlled clock gate, this clock should be represented in DT.
+ - "slave_bus"
+ The CPU/slave-bus (CSR) interface clock. This applies to any bus type;
+ APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other
+ buses).
+ - "master_bus"
+ The master bus interface clock. Only required in configurations that use a
+ separate clock for the master and slave bus interfaces. The HW signal name
+ is hclk_i (AHB) or aclk_i (AXI).
+ - "ptp_ref"
+ The PTP reference clock. The HW signal name is clk_ptp_ref_i.
+ - "phy_ref_clk"
+ This clock is deprecated and should not be used by new compatible values.
+ It is equivalent to "tx".
+ - "apb_pclk"
+ This clock is deprecated and should not be used by new compatible values.
+ It is equivalent to "slave_bus".
+
+ Note: Support for additional IP configurations may require adding the
+ following clocks to this list in the future: clk_rx_125_i, clk_tx_125_i,
+ clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk_revmii_rx_i, clk_revmii_tx_i.
+ Configurations exist where multiple similar clocks are used at once, e.g. all
+ of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i. For this reason it is best to
+ extend the binding with a separate clock-names entry for each of those RX
+ clocks, rather than repurposing the existing "rx" clock-names entry as a
+ generic/logical clock in a similar fashion to "master_bus" and "slave_bus".
+ This will allow easy support for configurations that support multiple PHY
+ interfaces using a mux, and hence need to have explicit control over
+ specific RX clocks.
+
+ The following compatible values require the following set of clocks:
+ - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
+ - "slave_bus"
+ - "master_bus"
+ - "rx"
+ - "tx"
+ - "ptp_ref"
+ - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
+ - "slave_bus"
+ - "master_bus"
+ - "tx"
+ - "ptp_ref"
+ - "snps,dwc-qos-ethernet-4.10" (deprecated):
+ - "phy_ref_clk"
+ - "apb_clk"
- interrupt-parent: Should be the phandle for the interrupt controller
that services interrupts for this device
- interrupts: Should contain the core's combined interrupt signal
- phy-mode: See ethernet.txt file in the same directory
+- resets: Phandle and reset specifiers for each entry in reset-names, in the
+ same order. See ../reset/reset.txt.
+- reset-names: May contain any/all of the following depending on the IP
+ configuration, in any order:
+ - "eqos". The reset to the entire module. The HW signal name is hreset_n
+ (AHB) or aresetn_i (AXI).
+
+ The following compatible values require the following set of resets:
+ (the reset properties may be omitted if empty)
+ - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
+ - "eqos".
+ - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
+ - None.
+ - "snps,dwc-qos-ethernet-4.10" (deprecated):
+ - None.
Optional properties:
- dma-coherent: Present if dma operations are coherent
- mac-address: See ethernet.txt in the same directory
- local-mac-address: See ethernet.txt in the same directory
+- phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY.
+ See ../gpio/gpio.txt.
- snps,en-lpi: If present it enables use of the AXI low-power interface
- snps,write-requests: Number of write requests that the AXI port can issue.
It depends on the SoC configuration.
reg = <0x40010000 0x4000>;
phy-handle = <&phy2>;
phy-mode = "gmii";
+ phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>;
snps,en-tx-lpi-clockgating;
snps,en-lpi;
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